pluto_hdl_adi/library/axi_ad9361
Rejeesh Kutty 1c386d4d34 hdlmake.pl- updates 2017-08-07 16:09:20 -04:00
..
altera axi_ad9361- altera/xilinx reconcile- may be broken- do not use 2017-07-24 16:28:50 -04:00
xilinx ad9361/sw- current sw requires clock edge swap 2017-07-31 14:48:25 -04:00
Makefile hdlmake.pl- updates 2017-08-07 16:09:20 -04:00
axi_ad9361.v axi_ad9361: Update the PPS receiver module 2017-08-02 16:38:23 +01:00
axi_ad9361_constr.sdc library/axi_ad9361: tdd false paths 2016-05-04 13:42:12 -04:00
axi_ad9361_constr.xdc axi_ad9361: Update constraint file 2017-08-04 16:20:33 +01:00
axi_ad9361_delay.tcl move/rename - delay script belongs to ad9361 2017-03-10 12:44:32 -05:00
axi_ad9361_hw.tcl library/ad9361- add pps module 2017-07-31 09:06:50 -04:00
axi_ad9361_ip.tcl axi_ad9361: Update constraint file 2017-08-04 16:20:33 +01:00
axi_ad9361_rx.v axi_ad9361: Update the PPS receiver module 2017-08-02 16:38:23 +01:00
axi_ad9361_rx_channel.v license: Add some clarification to the header license 2017-05-31 18:18:56 +03:00
axi_ad9361_rx_pnmon.v license: Add some clarification to the header license 2017-05-31 18:18:56 +03:00
axi_ad9361_tdd.v license: Add some clarification to the header license 2017-05-31 18:18:56 +03:00
axi_ad9361_tdd_if.v license: Add some clarification to the header license 2017-05-31 18:18:56 +03:00
axi_ad9361_tx.v axi_ad9361: Update the PPS receiver module 2017-08-02 16:38:23 +01:00
axi_ad9361_tx_channel.v hdl/library- fix syntax errors/synthesis warnings 2017-07-20 14:07:32 -04:00