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pluto_hdl_adi/library/xilinx/axi_adcfifo
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Adrian Costina b01cf35cf7 axi_adcfifo: Fix constraints to apply also to Ultrascale devices 
Used IS_SEQUENTIAL instead of PRIMITIVE_SUBGROUP==flop to identify ff related constraints
 		2018-09-07 17:44:47 +03:00
..
Makefile Move Altera IP core dependency tracking to library Makefiles 2018-04-11 15:09:54 +03:00
axi_adcfifo.v license: Fix a spelling mistake 2018-04-11 15:09:54 +03:00
axi_adcfifo_adc.v license: Fix a spelling mistake 2018-04-11 15:09:54 +03:00
axi_adcfifo_constr.xdc axi_adcfifo: Fix constraints to apply also to Ultrascale devices 2018-09-07 17:44:47 +03:00
axi_adcfifo_dma.v ad_mem_asym: Improve the implementation of the asymmetric RAM 2018-08-06 17:29:05 +03:00
axi_adcfifo_ip.tcl axi_adcfifo: Infer clock and reset signals 2018-04-11 15:09:54 +03:00
axi_adcfifo_rd.v license: Fix a spelling mistake 2018-04-11 15:09:54 +03:00
axi_adcfifo_wr.v util_axis_fifo: instantiate block ram in async mode 2018-04-11 15:09:54 +03:00