63 lines
3.1 KiB
Markdown
63 lines
3.1 KiB
Markdown
# Analog Devices JESD204B HDL Support
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## Licensing
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The ADI JESD204 Core is released under the following license, which is
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different than all other HDL cores in this repository.
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Please read this, and understand the freedoms and responsibilities you have by
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using this source code/core.
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The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
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This core is free software, you can use run, copy, study, change, ask questions
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about and improve this core. Distribution of source, or resulting binaries
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(including those inside an FPGA or ASIC) require you to release the source of
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the entire project (excluding the system libraries provide by the
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tools/compiler/FPGA vendor). These are the terms of the GNU General Public
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License version 2 as published by the Free Software Foundation.
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This core is distributed in the hope that it will be useful, but WITHOUT ANY
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WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A
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PARTICULAR PURPOSE. See the GNU General Public License for more details.
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You should have received a copy of the GNU General Public License version 2
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along with this source code, and binary. If not, see
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<http://www.gnu.org/licenses/>.
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Commercial licenses (with commercial support) of this JESD204 core are also
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available under terms different than the General Public License. (e.g. they do
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not require you to accompany any image (FPGA or ASIC) using the JESD204 core
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with any corresponding source code.) For these alternate terms you must
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purchase a license from Analog Devices Technology Licensing Office. Users
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interested in such a license should contact jesd204-licensing@analog.com for
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more information. This commercial license is sub-licensable (if you purchase
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chips from Analog Devices, incorporate them into your PCB level product, and
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purchase a JESD204 license, end users of your product will also have a license
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to use this core in a commercial setting without releasing their source code).
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In addition, we kindly ask you to acknowledge ADI in any program, application
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or publication in which you use this JESD204 HDL core. (You are not required to
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do so; it is up to your common sense to decide whether you want to comply with
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this request or not.) For general publications, we suggest referencing : “The
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design and implementation of the JESD204 HDL Core used in this project is
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copyright © 2016-2017, Analog Devices, Inc.”
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## Support
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Analog Devices will provide limited online support for anyone using the core
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with Analog Devices components (ADC, DAC, Clock, etc) via
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https://ez.analog.com/community/fpga under the GPL license. If you would like
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deterministic support when using this core with an ADI component, please
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investigate a commercial license. Using a non-ADI JESD204 device with this core
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is possible under the GPL, but Analog Devices will not help with issues you may
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encounter.
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## Documenation
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- [JESD204B overview](https://wiki.analog.com/resources/fpga/peripherals/jesd204)
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- [Analog Devices JESD204B Transmit Peripheral](https://wiki.analog.com/resources/fpga/peripherals/jesd204/axi_jesd204_tx)
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- [Analog Devices JESD204B Receive Peripheral](https://wiki.analog.com/resources/fpga/peripherals/jesd204/axi_jesd204_rx)
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