Adrian Costina 74b922f9f8 axi_*: Infer clock and reset signals of an IP ... A clock sink must be connected to clock source, and a reset sink to reset source, otherwise the tool will throw a synthesis warning. By properly inferring all the reset and clock signals of an IP, we can get rid of unwanted warning messages. The following IPs tcl script was updated: - axi_ad9434 - axi_hdmi_tx - util_cpack - util_adxcvr - axi_ad6676 - axi_ad9625 - axi_ad9379 - axi_ad9265 - util_tdd_sync - util_rfifo - util_wfifo - axi_ad9361 - axi_ad9467 - util_upack - axi_dacfifo - axi_ad9152 - axi_ad9680 - util_clkdiv - axi_ad9122 - axi_ad9684 - axi_mc_speed - axi_mc_current_monitor - axi_mc_controller - util_gmii_to_rgmii - util_adxcvr - axi_ad9379 - axi_hdmi - library - axi_fmcadc5_sync - util_adcfifo - util_mfifo - axi_jesd204_rx - axi_jesd204_tx - axi_ad9361 - axi_adxcvr_ip		2018-04-11 15:09:54 +03:00
..
Makefile	Make: Use $(MAKE) for recursive make commands	2018-03-07 07:40:19 +00:00
axi_jesd204_rx.v	jesd204: jesd204_rx: Don't expose internal states on the status interface	2017-08-24 17:42:44 +02:00
axi_jesd204_rx_constr.sdc	jesd204: Add Altera/Intel IP support	2017-08-21 11:09:42 +02:00
axi_jesd204_rx_constr.xdc	jesd204: ilas_mem: Rework to be more Altera friendly	2017-08-21 11:05:16 +02:00
axi_jesd204_rx_hw.tcl	jesd204: jesd204_rx: Don't expose internal states on the status interface	2017-08-24 17:42:44 +02:00
axi_jesd204_rx_ip.tcl	axi_*: Infer clock and reset signals of an IP	2018-04-11 15:09:54 +03:00
jesd204_up_ilas_mem.v	jesd204: ilas_mem: Rework to be more Altera friendly	2017-08-21 11:05:16 +02:00
jesd204_up_rx.v	jesd204: jesd204_rx: Don't expose internal states on the status interface	2017-08-24 17:42:44 +02:00
jesd204_up_rx_lane.v	jesd204: ilas_mem: Rework to be more Altera friendly	2017-08-21 11:05:16 +02:00