684 lines
20 KiB
Verilog
Executable File
684 lines
20 KiB
Verilog
Executable File
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2011(c) Analog Devices, Inc.
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//
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without modification,
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// are permitted provided that the following conditions are met:
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// - Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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// - Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in
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// the documentation and/or other materials provided with the
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// distribution.
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// - Neither the name of Analog Devices, Inc. nor the names of its
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// contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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// - The use of this software may or may not infringe the patent rights
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// of one or more patent holders. This license does not release you
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// from the requirement that you obtain separate licenses from these
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// patent holders to use this software.
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// - Use of the software either in source or binary form, must be run
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// on or directly connected to an Analog Devices Inc. component.
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//
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// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
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// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
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// PARTICULAR PURPOSE ARE DISCLAIMED.
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//
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// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
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// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
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// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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// This interface includes both the transmit and receive components -
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// They both uses the same clock (sourced from the receiving side).
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`timescale 1ns/100ps
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module axi_ad9361_dev_if (
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// physical interface (receive)
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rx_clk_in_p,
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rx_clk_in_n,
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rx_frame_in_p,
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rx_frame_in_n,
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rx_data_in_p,
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rx_data_in_n,
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// physical interface (transmit)
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tx_clk_out_p,
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tx_clk_out_n,
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tx_frame_out_p,
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tx_frame_out_n,
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tx_data_out_p,
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tx_data_out_n,
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// clock (common to both receive and transmit)
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clk,
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// receive data path interface
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adc_valid,
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adc_data_i1,
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adc_data_q1,
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adc_data_i2,
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adc_data_q2,
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adc_status,
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adc_r1_mode,
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// transmit data path interface
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dac_valid,
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dac_data_i1,
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dac_data_q1,
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dac_data_i2,
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dac_data_q2,
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dac_r1_mode,
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// delay control signals
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delay_clk,
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delay_rst,
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delay_sel,
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delay_rwn,
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delay_addr,
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delay_wdata,
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delay_rdata,
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delay_ack_t,
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delay_locked,
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// chipscope signals
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dev_dbg_trigger,
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dev_dbg_data);
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// this parameter controls the buffer type based on the target device.
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parameter PCORE_BUFTYPE = 0;
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parameter PCORE_IODELAY_GROUP = "dev_if_delay_group";
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localparam PCORE_7SERIES = 0;
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localparam PCORE_VIRTEX6 = 1;
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// physical interface (receive)
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input rx_clk_in_p;
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input rx_clk_in_n;
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input rx_frame_in_p;
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input rx_frame_in_n;
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input [ 5:0] rx_data_in_p;
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input [ 5:0] rx_data_in_n;
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// physical interface (transmit)
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output tx_clk_out_p;
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output tx_clk_out_n;
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output tx_frame_out_p;
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output tx_frame_out_n;
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output [ 5:0] tx_data_out_p;
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output [ 5:0] tx_data_out_n;
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// clock (common to both receive and transmit)
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output clk;
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// receive data path interface
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output adc_valid;
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output [11:0] adc_data_i1;
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output [11:0] adc_data_q1;
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output [11:0] adc_data_i2;
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output [11:0] adc_data_q2;
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output adc_status;
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input adc_r1_mode;
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// transmit data path interface
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input dac_valid;
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input [11:0] dac_data_i1;
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input [11:0] dac_data_q1;
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input [11:0] dac_data_i2;
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input [11:0] dac_data_q2;
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input dac_r1_mode;
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// delay control signals
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input delay_clk;
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input delay_rst;
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input delay_sel;
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input delay_rwn;
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input [ 7:0] delay_addr;
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input [ 4:0] delay_wdata;
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output [ 4:0] delay_rdata;
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output delay_ack_t;
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output delay_locked;
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// chipscope signals
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output [ 3:0] dev_dbg_trigger;
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output [297:0] dev_dbg_data;
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// internal registers
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reg [ 5:0] rx_data_n = 'd0;
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reg rx_frame_n = 'd0;
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reg [11:0] rx_data = 'd0;
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reg [ 1:0] rx_frame = 'd0;
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reg [11:0] rx_data_d = 'd0;
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reg [ 1:0] rx_frame_d = 'd0;
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reg rx_error_r1 = 'd0;
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reg rx_valid_r1 = 'd0;
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reg [11:0] rx_data_i_r1 = 'd0;
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reg [11:0] rx_data_q_r1 = 'd0;
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reg rx_error_r2 = 'd0;
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reg rx_valid_r2 = 'd0;
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reg [11:0] rx_data_i1_r2 = 'd0;
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reg [11:0] rx_data_q1_r2 = 'd0;
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reg [11:0] rx_data_i2_r2 = 'd0;
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reg [11:0] rx_data_q2_r2 = 'd0;
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reg adc_valid = 'd0;
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reg [11:0] adc_data_i1 = 'd0;
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reg [11:0] adc_data_q1 = 'd0;
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reg [11:0] adc_data_i2 = 'd0;
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reg [11:0] adc_data_q2 = 'd0;
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reg adc_status = 'd0;
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reg [ 2:0] tx_data_cnt = 'd0;
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reg [11:0] tx_data_i1_d = 'd0;
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reg [11:0] tx_data_q1_d = 'd0;
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reg [11:0] tx_data_i2_d = 'd0;
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reg [11:0] tx_data_q2_d = 'd0;
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reg tx_frame = 'd0;
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reg [ 5:0] tx_data_p = 'd0;
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reg [ 5:0] tx_data_n = 'd0;
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reg [ 6:0] delay_ld = 'd0;
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reg [ 4:0] delay_rdata = 'd0;
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reg delay_ack_t = 'd0;
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// internal signals
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wire [ 3:0] rx_frame_s;
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wire [ 3:0] tx_data_sel_s;
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wire [ 4:0] delay_rdata_s[6:0];
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wire [ 5:0] rx_data_ibuf_s;
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wire [ 5:0] rx_data_idelay_s;
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wire [ 5:0] rx_data_p_s;
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wire [ 5:0] rx_data_n_s;
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wire rx_frame_ibuf_s;
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wire rx_frame_idelay_s;
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wire rx_frame_p_s;
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wire rx_frame_n_s;
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wire [ 5:0] tx_data_oddr_s;
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wire tx_frame_oddr_s;
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wire tx_clk_oddr_s;
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wire clk_ibuf_s;
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genvar l_inst;
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// device debug signals
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assign dev_dbg_trigger[0] = rx_frame[0];
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assign dev_dbg_trigger[1] = rx_frame[1];
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assign dev_dbg_trigger[2] = tx_frame;
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assign dev_dbg_trigger[3] = adc_status;
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assign dev_dbg_data[ 5: 0] = tx_data_n;
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assign dev_dbg_data[ 11: 6] = tx_data_p;
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assign dev_dbg_data[ 23: 12] = tx_data_i1_d;
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assign dev_dbg_data[ 35: 24] = tx_data_q1_d;
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assign dev_dbg_data[ 47: 36] = tx_data_i2_d;
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assign dev_dbg_data[ 59: 48] = tx_data_q2_d;
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assign dev_dbg_data[ 63: 60] = tx_data_sel_s;
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assign dev_dbg_data[ 66: 64] = tx_data_cnt;
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assign dev_dbg_data[ 67: 67] = tx_frame;
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assign dev_dbg_data[ 68: 68] = dac_r1_mode;
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assign dev_dbg_data[ 69: 69] = dac_valid;
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assign dev_dbg_data[ 81: 70] = dac_data_i1;
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assign dev_dbg_data[ 93: 82] = dac_data_q1;
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assign dev_dbg_data[105: 94] = dac_data_i2;
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assign dev_dbg_data[117:106] = dac_data_q2;
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assign dev_dbg_data[118:118] = rx_frame_p_s;
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assign dev_dbg_data[119:119] = rx_frame_n_s;
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assign dev_dbg_data[120:120] = rx_frame_n;
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assign dev_dbg_data[122:121] = rx_frame;
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assign dev_dbg_data[124:123] = rx_frame_d;
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assign dev_dbg_data[128:125] = rx_frame_s;
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assign dev_dbg_data[134:129] = rx_data_p_s;
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assign dev_dbg_data[140:135] = rx_data_n_s;
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assign dev_dbg_data[146:141] = rx_data_n;
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assign dev_dbg_data[158:147] = rx_data;
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assign dev_dbg_data[170:159] = rx_data_d;
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assign dev_dbg_data[171:171] = rx_error_r1;
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assign dev_dbg_data[172:172] = rx_valid_r1;
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assign dev_dbg_data[184:173] = rx_data_i_r1;
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assign dev_dbg_data[196:185] = rx_data_q_r1;
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assign dev_dbg_data[197:197] = rx_error_r2;
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assign dev_dbg_data[198:198] = rx_valid_r2;
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assign dev_dbg_data[210:199] = rx_data_i1_r2;
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assign dev_dbg_data[222:211] = rx_data_q1_r2;
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assign dev_dbg_data[234:223] = rx_data_i2_r2;
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assign dev_dbg_data[246:235] = rx_data_q2_r2;
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assign dev_dbg_data[247:247] = adc_r1_mode;
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assign dev_dbg_data[248:248] = adc_status;
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assign dev_dbg_data[249:249] = adc_valid;
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assign dev_dbg_data[261:250] = adc_data_i1;
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assign dev_dbg_data[273:262] = adc_data_q1;
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assign dev_dbg_data[285:274] = adc_data_i2;
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assign dev_dbg_data[297:286] = adc_data_q2;
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// receive data path interface
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assign rx_frame_s = {rx_frame_d, rx_frame};
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always @(posedge clk) begin
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rx_data_n <= rx_data_n_s;
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rx_frame_n <= rx_frame_n_s;
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rx_data <= {rx_data_n, rx_data_p_s};
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rx_frame <= {rx_frame_n, rx_frame_p_s};
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rx_data_d <= rx_data;
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rx_frame_d <= rx_frame;
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end
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// receive data path for single rf, frame is expected to qualify i/q msb only
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always @(posedge clk) begin
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rx_error_r1 <= ((rx_frame_s == 4'b1100) || (rx_frame_s == 4'b0011)) ? 1'b0 : 1'b1;
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rx_valid_r1 <= (rx_frame_s == 4'b1100) ? 1'b1 : 1'b0;
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if (rx_frame_s == 4'b1100) begin
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rx_data_i_r1 <= {rx_data_d[11:6], rx_data[11:6]};
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rx_data_q_r1 <= {rx_data_d[ 5:0], rx_data[ 5:0]};
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end
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end
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// receive data path for dual rf, frame is expected to qualify i/q msb and lsb for rf-1 only
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always @(posedge clk) begin
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rx_error_r2 <= ((rx_frame_s == 4'b1111) || (rx_frame_s == 4'b1100) ||
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(rx_frame_s == 4'b0000) || (rx_frame_s == 4'b0011)) ? 1'b0 : 1'b1;
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rx_valid_r2 <= (rx_frame_s == 4'b0000) ? 1'b1 : 1'b0;
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if (rx_frame_s == 4'b1111) begin
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rx_data_i1_r2 <= {rx_data_d[11:6], rx_data[11:6]};
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rx_data_q1_r2 <= {rx_data_d[ 5:0], rx_data[ 5:0]};
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end
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if (rx_frame_s == 4'b0000) begin
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rx_data_i2_r2 <= {rx_data_d[11:6], rx_data[11:6]};
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rx_data_q2_r2 <= {rx_data_d[ 5:0], rx_data[ 5:0]};
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end
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end
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// receive data path mux
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always @(posedge clk) begin
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if (adc_r1_mode == 1'b1) begin
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adc_valid <= rx_valid_r1;
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adc_data_i1 <= rx_data_i_r1;
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adc_data_q1 <= rx_data_q_r1;
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adc_data_i2 <= 12'd0;
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adc_data_q2 <= 12'd0;
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adc_status <= ~rx_error_r1;
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end else begin
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adc_valid <= rx_valid_r2;
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adc_data_i1 <= rx_data_i1_r2;
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adc_data_q1 <= rx_data_q1_r2;
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adc_data_i2 <= rx_data_i2_r2;
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adc_data_q2 <= rx_data_q2_r2;
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adc_status <= ~rx_error_r2;
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end
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end
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// transmit data path mux (reverse of what receive does above)
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// the count simply selets the data muxing on the ddr outputs
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assign tx_data_sel_s = {tx_data_cnt[2], dac_r1_mode, tx_data_cnt[1:0]};
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always @(posedge clk) begin
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if (dac_valid == 1'b1) begin
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tx_data_cnt <= 3'b100;
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end else if (tx_data_cnt[2] == 1'b1) begin
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tx_data_cnt <= tx_data_cnt + 1'b1;
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end
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if (dac_valid == 1'b1) begin
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tx_data_i1_d <= dac_data_i1;
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tx_data_q1_d <= dac_data_q1;
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tx_data_i2_d <= dac_data_i2;
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tx_data_q2_d <= dac_data_q2;
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end
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case (tx_data_sel_s)
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4'b1111: begin
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tx_frame <= 1'b0;
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tx_data_p <= tx_data_i1_d[ 5:0];
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tx_data_n <= tx_data_q1_d[ 5:0];
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end
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4'b1110: begin
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tx_frame <= 1'b1;
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tx_data_p <= tx_data_i1_d[11:6];
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tx_data_n <= tx_data_q1_d[11:6];
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end
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4'b1101: begin
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tx_frame <= 1'b0;
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tx_data_p <= tx_data_i1_d[ 5:0];
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tx_data_n <= tx_data_q1_d[ 5:0];
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end
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4'b1100: begin
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tx_frame <= 1'b1;
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tx_data_p <= tx_data_i1_d[11:6];
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tx_data_n <= tx_data_q1_d[11:6];
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end
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4'b1011: begin
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tx_frame <= 1'b0;
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tx_data_p <= tx_data_i2_d[ 5:0];
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tx_data_n <= tx_data_q2_d[ 5:0];
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end
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4'b1010: begin
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tx_frame <= 1'b0;
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tx_data_p <= tx_data_i2_d[11:6];
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tx_data_n <= tx_data_q2_d[11:6];
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end
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4'b1001: begin
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tx_frame <= 1'b1;
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tx_data_p <= tx_data_i1_d[ 5:0];
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tx_data_n <= tx_data_q1_d[ 5:0];
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end
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4'b1000: begin
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tx_frame <= 1'b1;
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tx_data_p <= tx_data_i1_d[11:6];
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tx_data_n <= tx_data_q1_d[11:6];
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end
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default: begin
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tx_frame <= 1'b0;
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tx_data_p <= 6'd0;
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tx_data_n <= 6'd0;
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end
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endcase
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end
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// delay write interface, each delay element can be individually
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// addressed, and a delay value can be directly loaded (no inc/dec stuff)
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always @(posedge delay_clk) begin
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if ((delay_sel == 1'b1) && (delay_rwn == 1'b0)) begin
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case (delay_addr)
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8'h06: delay_ld <= 7'h40;
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8'h05: delay_ld <= 7'h20;
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8'h04: delay_ld <= 7'h10;
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8'h03: delay_ld <= 7'h08;
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8'h02: delay_ld <= 7'h04;
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8'h01: delay_ld <= 7'h02;
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8'h00: delay_ld <= 7'h01;
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default: delay_ld <= 7'h00;
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endcase
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end else begin
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delay_ld <= 7'h00;
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end
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end
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// delay read interface, a delay ack toggle is used to transfer data to the
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// processor side- delay locked is independently transferred
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always @(posedge delay_clk) begin
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case (delay_addr)
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8'h06: delay_rdata <= delay_rdata_s[6];
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8'h05: delay_rdata <= delay_rdata_s[5];
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8'h04: delay_rdata <= delay_rdata_s[4];
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8'h03: delay_rdata <= delay_rdata_s[3];
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8'h02: delay_rdata <= delay_rdata_s[2];
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8'h01: delay_rdata <= delay_rdata_s[1];
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8'h00: delay_rdata <= delay_rdata_s[0];
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default: delay_rdata <= 5'd0;
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endcase
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if (delay_sel == 1'b1) begin
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delay_ack_t <= ~delay_ack_t;
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end
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end
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// delay controller
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|
|
|
(* IODELAY_GROUP = PCORE_IODELAY_GROUP *)
|
|
IDELAYCTRL i_delay_ctrl (
|
|
.RST (delay_rst),
|
|
.REFCLK (delay_clk),
|
|
.RDY (delay_locked));
|
|
|
|
// receive data interface, ibuf -> idelay -> iddr
|
|
|
|
generate
|
|
for (l_inst = 0; l_inst <= 5; l_inst = l_inst + 1) begin: g_rx_data
|
|
|
|
IBUFDS i_rx_data_ibuf (
|
|
.I (rx_data_in_p[l_inst]),
|
|
.IB (rx_data_in_n[l_inst]),
|
|
.O (rx_data_ibuf_s[l_inst]));
|
|
|
|
if (PCORE_BUFTYPE == PCORE_VIRTEX6) begin
|
|
(* IODELAY_GROUP = PCORE_IODELAY_GROUP *)
|
|
IODELAYE1 #(
|
|
.CINVCTRL_SEL ("FALSE"),
|
|
.DELAY_SRC ("I"),
|
|
.HIGH_PERFORMANCE_MODE ("TRUE"),
|
|
.IDELAY_TYPE ("VAR_LOADABLE"),
|
|
.IDELAY_VALUE (0),
|
|
.ODELAY_TYPE ("FIXED"),
|
|
.ODELAY_VALUE (0),
|
|
.REFCLK_FREQUENCY (200.0),
|
|
.SIGNAL_PATTERN ("DATA"))
|
|
i_rx_data_idelay (
|
|
.T (1'b1),
|
|
.CE (1'b0),
|
|
.INC (1'b0),
|
|
.CLKIN (1'b0),
|
|
.DATAIN (1'b0),
|
|
.ODATAIN (1'b0),
|
|
.CINVCTRL (1'b0),
|
|
.C (delay_clk),
|
|
.IDATAIN (rx_data_ibuf_s[l_inst]),
|
|
.DATAOUT (rx_data_idelay_s[l_inst]),
|
|
.RST (delay_ld[l_inst]),
|
|
.CNTVALUEIN (delay_wdata),
|
|
.CNTVALUEOUT (delay_rdata_s[l_inst]));
|
|
end else begin
|
|
(* IODELAY_GROUP = PCORE_IODELAY_GROUP *)
|
|
IDELAYE2 #(
|
|
.CINVCTRL_SEL ("FALSE"),
|
|
.DELAY_SRC ("IDATAIN"),
|
|
.HIGH_PERFORMANCE_MODE ("FALSE"),
|
|
.IDELAY_TYPE ("VAR_LOAD"),
|
|
.IDELAY_VALUE (0),
|
|
.REFCLK_FREQUENCY (200.0),
|
|
.PIPE_SEL ("FALSE"),
|
|
.SIGNAL_PATTERN ("DATA"))
|
|
i_rx_data_idelay (
|
|
.CE (1'b0),
|
|
.INC (1'b0),
|
|
.DATAIN (1'b0),
|
|
.LDPIPEEN (1'b0),
|
|
.CINVCTRL (1'b0),
|
|
.REGRST (1'b0),
|
|
.C (delay_clk),
|
|
.IDATAIN (rx_data_ibuf_s[l_inst]),
|
|
.DATAOUT (rx_data_idelay_s[l_inst]),
|
|
.LD (delay_ld[l_inst]),
|
|
.CNTVALUEIN (delay_wdata),
|
|
.CNTVALUEOUT (delay_rdata_s[l_inst]));
|
|
end
|
|
|
|
IDDR #(
|
|
.DDR_CLK_EDGE ("SAME_EDGE_PIPELINED"),
|
|
.INIT_Q1 (1'b0),
|
|
.INIT_Q2 (1'b0),
|
|
.SRTYPE ("ASYNC"))
|
|
i_rx_data_iddr (
|
|
.CE (1'b1),
|
|
.R (1'b0),
|
|
.S (1'b0),
|
|
.C (clk),
|
|
.D (rx_data_idelay_s[l_inst]),
|
|
.Q1 (rx_data_p_s[l_inst]),
|
|
.Q2 (rx_data_n_s[l_inst]));
|
|
|
|
end
|
|
endgenerate
|
|
|
|
// receive frame interface, ibuf -> idelay -> iddr
|
|
|
|
IBUFDS i_rx_frame_ibuf (
|
|
.I (rx_frame_in_p),
|
|
.IB (rx_frame_in_n),
|
|
.O (rx_frame_ibuf_s));
|
|
|
|
generate
|
|
if (PCORE_BUFTYPE == PCORE_VIRTEX6) begin
|
|
(* IODELAY_GROUP = PCORE_IODELAY_GROUP *)
|
|
IODELAYE1 #(
|
|
.CINVCTRL_SEL ("FALSE"),
|
|
.DELAY_SRC ("I"),
|
|
.HIGH_PERFORMANCE_MODE ("TRUE"),
|
|
.IDELAY_TYPE ("VAR_LOADABLE"),
|
|
.IDELAY_VALUE (0),
|
|
.ODELAY_TYPE ("FIXED"),
|
|
.ODELAY_VALUE (0),
|
|
.REFCLK_FREQUENCY (200.0),
|
|
.SIGNAL_PATTERN ("DATA"))
|
|
i_rx_frame_idelay (
|
|
.T (1'b1),
|
|
.CE (1'b0),
|
|
.INC (1'b0),
|
|
.CLKIN (1'b0),
|
|
.DATAIN (1'b0),
|
|
.ODATAIN (1'b0),
|
|
.CINVCTRL (1'b0),
|
|
.C (delay_clk),
|
|
.IDATAIN (rx_frame_ibuf_s),
|
|
.DATAOUT (rx_frame_idelay_s),
|
|
.RST (delay_ld[6]),
|
|
.CNTVALUEIN (delay_wdata),
|
|
.CNTVALUEOUT (delay_rdata_s[6]));
|
|
end else begin
|
|
(* IODELAY_GROUP = PCORE_IODELAY_GROUP *)
|
|
IDELAYE2 #(
|
|
.CINVCTRL_SEL ("FALSE"),
|
|
.DELAY_SRC ("IDATAIN"),
|
|
.HIGH_PERFORMANCE_MODE ("FALSE"),
|
|
.IDELAY_TYPE ("VAR_LOAD"),
|
|
.IDELAY_VALUE (0),
|
|
.REFCLK_FREQUENCY (200.0),
|
|
.PIPE_SEL ("FALSE"),
|
|
.SIGNAL_PATTERN ("DATA"))
|
|
i_rx_frame_idelay (
|
|
.CE (1'b0),
|
|
.INC (1'b0),
|
|
.DATAIN (1'b0),
|
|
.LDPIPEEN (1'b0),
|
|
.CINVCTRL (1'b0),
|
|
.REGRST (1'b0),
|
|
.C (delay_clk),
|
|
.IDATAIN (rx_frame_ibuf_s),
|
|
.DATAOUT (rx_frame_idelay_s),
|
|
.LD (delay_ld[6]),
|
|
.CNTVALUEIN (delay_wdata),
|
|
.CNTVALUEOUT (delay_rdata_s[6]));
|
|
end
|
|
endgenerate
|
|
|
|
IDDR #(
|
|
.DDR_CLK_EDGE ("SAME_EDGE_PIPELINED"),
|
|
.INIT_Q1 (1'b0),
|
|
.INIT_Q2 (1'b0),
|
|
.SRTYPE ("ASYNC"))
|
|
i_rx_frame_iddr (
|
|
.CE (1'b1),
|
|
.R (1'b0),
|
|
.S (1'b0),
|
|
.C (clk),
|
|
.D (rx_frame_idelay_s),
|
|
.Q1 (rx_frame_p_s),
|
|
.Q2 (rx_frame_n_s));
|
|
|
|
// transmit data interface, oddr -> obuf
|
|
|
|
generate
|
|
for (l_inst = 0; l_inst <= 5; l_inst = l_inst + 1) begin: g_tx_data
|
|
|
|
ODDR #(
|
|
.DDR_CLK_EDGE ("SAME_EDGE"),
|
|
.INIT (1'b0),
|
|
.SRTYPE ("ASYNC"))
|
|
i_tx_data_oddr (
|
|
.CE (1'b1),
|
|
.R (1'b0),
|
|
.S (1'b0),
|
|
.C (clk),
|
|
.D1 (tx_data_p[l_inst]),
|
|
.D2 (tx_data_n[l_inst]),
|
|
.Q (tx_data_oddr_s[l_inst]));
|
|
|
|
OBUFDS i_tx_data_obuf (
|
|
.I (tx_data_oddr_s[l_inst]),
|
|
.O (tx_data_out_p[l_inst]),
|
|
.OB (tx_data_out_n[l_inst]));
|
|
|
|
end
|
|
endgenerate
|
|
|
|
// transmit frame interface, oddr -> obuf
|
|
|
|
ODDR #(
|
|
.DDR_CLK_EDGE ("SAME_EDGE"),
|
|
.INIT (1'b0),
|
|
.SRTYPE ("ASYNC"))
|
|
i_tx_frame_oddr (
|
|
.CE (1'b1),
|
|
.R (1'b0),
|
|
.S (1'b0),
|
|
.C (clk),
|
|
.D1 (tx_frame),
|
|
.D2 (tx_frame),
|
|
.Q (tx_frame_oddr_s));
|
|
|
|
OBUFDS i_tx_frame_obuf (
|
|
.I (tx_frame_oddr_s),
|
|
.O (tx_frame_out_p),
|
|
.OB (tx_frame_out_n));
|
|
|
|
// transmit clock interface, oddr -> obuf
|
|
|
|
ODDR #(
|
|
.DDR_CLK_EDGE ("SAME_EDGE"),
|
|
.INIT (1'b0),
|
|
.SRTYPE ("ASYNC"))
|
|
i_tx_clk_oddr (
|
|
.CE (1'b1),
|
|
.R (1'b0),
|
|
.S (1'b0),
|
|
.C (clk),
|
|
.D1 (1'b0),
|
|
.D2 (1'b1),
|
|
.Q (tx_clk_oddr_s));
|
|
|
|
OBUFDS i_tx_clk_obuf (
|
|
.I (tx_clk_oddr_s),
|
|
.O (tx_clk_out_p),
|
|
.OB (tx_clk_out_n));
|
|
|
|
// device clock interface (receive clock)
|
|
|
|
IBUFGDS i_rx_clk_ibuf (
|
|
.I (rx_clk_in_p),
|
|
.IB (rx_clk_in_n),
|
|
.O (clk_ibuf_s));
|
|
|
|
BUFG i_clk_gbuf (
|
|
.I (clk_ibuf_s),
|
|
.O (clk));
|
|
|
|
endmodule
|
|
|
|
// ***************************************************************************
|
|
// ***************************************************************************
|