174 lines
5.9 KiB
Verilog
Executable File
174 lines
5.9 KiB
Verilog
Executable File
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2011(c) Analog Devices, Inc.
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//
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without modification,
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// are permitted provided that the following conditions are met:
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// - Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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// - Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in
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// the documentation and/or other materials provided with the
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// distribution.
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// - Neither the name of Analog Devices, Inc. nor the names of its
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// contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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// - The use of this software may or may not infringe the patent rights
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// of one or more patent holders. This license does not release you
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// from the requirement that you obtain separate licenses from these
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// patent holders to use this software.
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// - Use of the software either in source or binary form, must be run
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// on or directly connected to an Analog Devices Inc. component.
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//
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// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
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// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
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// PARTICULAR PURPOSE ARE DISCLAIMED.
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//
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// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
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// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
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// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module axi_ad9361_tx_channel (
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// dac interface
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dac_clk,
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dac_rst,
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dac_dds_data,
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// processor interface
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dac_dds_enable,
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dac_dds_data_enable,
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dac_dds_format,
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dac_dds_pattenb,
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dac_lb_enb,
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dac_pn_enb,
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// bus interface
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up_rstn,
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up_clk,
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up_sel,
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up_wr,
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up_addr,
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up_wdata,
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up_rdata,
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up_ack);
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// parameters
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parameter CHID = 32'h0;
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parameter DP_DISABLE = 0;
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// dac interface
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input dac_clk;
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input dac_rst;
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output [15:0] dac_dds_data;
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// processor interface
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input dac_dds_enable;
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input dac_dds_data_enable;
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input dac_dds_format;
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input dac_dds_pattenb;
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output dac_lb_enb;
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output dac_pn_enb;
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// bus interface
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input up_rstn;
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input up_clk;
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input up_sel;
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input up_wr;
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input [13:0] up_addr;
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input [31:0] up_wdata;
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output [31:0] up_rdata;
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output up_ack;
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// internal signals
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wire [15:0] dac_dds_patt_1_s;
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wire [15:0] dac_dds_init_1_s;
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wire [15:0] dac_dds_incr_1_s;
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wire [15:0] dac_dds_scale_1_s;
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wire [15:0] dac_dds_patt_2_s;
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wire [15:0] dac_dds_init_2_s;
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wire [15:0] dac_dds_incr_2_s;
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wire [15:0] dac_dds_scale_2_s;
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// single channel dds
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axi_ad9361_tx_dds #(.DP_DISABLE(DP_DISABLE)) i_tx_dds (
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.dac_clk (dac_clk),
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.dac_rst (dac_rst),
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.dac_dds_data (dac_dds_data),
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.dac_dds_enable (dac_dds_enable),
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.dac_dds_data_enable (dac_dds_data_enable),
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.dac_dds_format (dac_dds_format),
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.dac_dds_pattenb (dac_dds_pattenb),
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.dac_dds_patt_1 (dac_dds_patt_1_s),
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.dac_dds_init_1 (dac_dds_init_1_s),
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.dac_dds_incr_1 (dac_dds_incr_1_s),
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.dac_dds_scale_1 (dac_dds_scale_1_s),
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.dac_dds_patt_2 (dac_dds_patt_2_s),
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.dac_dds_init_2 (dac_dds_init_2_s),
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.dac_dds_incr_2 (dac_dds_incr_2_s),
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.dac_dds_scale_2 (dac_dds_scale_2_s));
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// single channel processor
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up_dac_channel #(.PCORE_DAC_CHID(CHID)) i_up_dac_channel (
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.dac_clk (dac_clk),
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.dac_rst (dac_rst),
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.dac_dds_scale_1 (dac_dds_scale_1_s),
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.dac_dds_init_1 (dac_dds_init_1_s),
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.dac_dds_incr_1 (dac_dds_incr_1_s),
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.dac_dds_scale_2 (dac_dds_scale_2_s),
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.dac_dds_init_2 (dac_dds_init_2_s),
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.dac_dds_incr_2 (dac_dds_incr_2_s),
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.dac_dds_patt_1 (dac_dds_patt_1_s),
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.dac_dds_patt_2 (dac_dds_patt_2_s),
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.dac_dds_sel (),
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.dac_lb_enb (dac_lb_enb),
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.dac_pn_enb (dac_pn_enb),
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.up_usr_datatype_be (),
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.up_usr_datatype_signed (),
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.up_usr_datatype_shift (),
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.up_usr_datatype_total_bits (),
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.up_usr_datatype_bits (),
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.up_usr_interpolation_m (),
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.up_usr_interpolation_n (),
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.dac_usr_datatype_be (1'b0),
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.dac_usr_datatype_signed (1'b1),
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.dac_usr_datatype_shift (8'd0),
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.dac_usr_datatype_total_bits (8'd16),
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.dac_usr_datatype_bits (8'd16),
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.dac_usr_interpolation_m (16'd1),
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.dac_usr_interpolation_n (16'd1),
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.up_rstn (up_rstn),
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.up_clk (up_clk),
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.up_sel (up_sel),
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.up_wr (up_wr),
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.up_addr (up_addr),
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.up_wdata (up_wdata),
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.up_rdata (up_rdata),
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.up_ack (up_ack));
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endmodule
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// ***************************************************************************
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// ***************************************************************************
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