235 lines
8.5 KiB
Verilog
Executable File
235 lines
8.5 KiB
Verilog
Executable File
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2013(c) Analog Devices, Inc.
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//
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without modification,
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// are permitted provided that the following conditions are met:
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// - Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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// - Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in
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// the documentation and/or other materials provided with the
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// distribution.
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// - Neither the name of Analog Devices, Inc. nor the names of its
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// contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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// - The use of this software may or may not infringe the patent rights
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// of one or more patent holders. This license does not release you
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// from the requirement that you obtain separate licenses from these
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// patent holders to use this software.
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// - Use of the software either in source or binary form, must be run
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// on or directly connected to an Analog Devices Inc. component.
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//
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// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
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// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
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// PARTICULAR PURPOSE ARE DISCLAIMED.
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//
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// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
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// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
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// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// ***************************************************************************
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// ***************************************************************************
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module control_registers
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(
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//bus interface
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input up_rstn,
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input up_clk,
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input up_sel,
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input up_wr,
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input [13:0] up_addr,
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input [31:0] up_wdata,
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output reg [31:0] up_rdata,
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output reg up_ack,
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//control
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input [31:0] err_i,
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output [31:0] pwm_open_o,
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output [31:0] reference_speed_o,
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output [31:0] kp_o,
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output [31:0] ki_o,
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output [31:0] kd_o,
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output [31:0] kp1_o,
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output [31:0] ki1_o,
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output [31:0] kd1_o,
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output run_o,
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output break_o,
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output dir_o,
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output star_delta_o,
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output [1:0] sensors_o,
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output [10:0] gpo_o,
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output oloop_matlab_o,
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output calibrate_adcs_o
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);
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//------------------------------------------------------------------------------
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//----------- Registers Declarations -------------------------------------------
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//------------------------------------------------------------------------------
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//internal registers
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reg [31:0] control_r;
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reg [31:0] reference_speed_r;
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reg [31:0] kp_r;
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reg [31:0] ki_r;
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reg [31:0] kp1_r;
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reg [31:0] ki1_r;
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reg [31:0] kd1_r;
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reg [31:0] pwm_open_r;
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reg [31:0] pwm_break_r;
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reg [31:0] status_r;
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reg [31:0] reserved_r1;
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reg [31:0] kd_r;
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reg [10:0] gpo_r;
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//------------------------------------------------------------------------------
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//----------- Wires Declarations -----------------------------------------------
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//------------------------------------------------------------------------------
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//internal signals
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wire up_sel_s;
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wire up_wr_s;
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//------------------------------------------------------------------------------
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//----------- Assign/Always Blocks ---------------------------------------------
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//------------------------------------------------------------------------------
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assign up_sel_s = (up_addr[13:4] == 10'h00) ? up_sel : 1'b0;
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assign up_wr_s = up_sel_s & up_wr;
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assign run_o = control_r[0]; // Run the motor
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assign break_o = control_r[2]; // Activate the Break circuit
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assign dir_o = control_r[3]; // 0 CCW, 1 CW
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assign star_delta_o = control_r[4]; // Select between star [0] or delta [1] controller
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assign sensors_o = control_r[9:8]; // Select between Hall[00] and BEMF[01] sensors
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assign calibrate_adcs_o = control_r[16];
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assign oloop_matlab_o = control_r[12]; // Select between open loop control [0] and matlab control [1]
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assign gpo_o = control_r[30:20];
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assign pwm_open_o = pwm_open_r; // PWM value, for open loop control
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assign reference_speed_o = reference_speed_r;
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assign kp_o = kp_r; // KP controller parameter
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assign ki_o = ki_r; // KI controller parameter
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assign kd_o = kd_r; // KD controller parameter
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assign kp1_o = kp1_r;
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assign kd1_o = kd1_r;
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assign ki1_o = ki1_r;
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// processor write interface
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always @(negedge up_rstn or posedge up_clk)
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begin
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if (up_rstn == 0)
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begin
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control_r <= 'h0;
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reference_speed_r <= 'd1000;
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kp_r <= 'd6554;
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ki_r <= 'd26;
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kd_r <= 'd655360;
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kp1_r <= 'd0;
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ki1_r <= 'd0;
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kd1_r <= 'd0;
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pwm_open_r <= 'h5ff;
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pwm_break_r <= 'd0;
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status_r <= 'd0;
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end
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else
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begin
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if ((up_wr_s == 1'b1) && (up_addr[3:0] == 4'h3))
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begin
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reserved_r1 <= up_wdata;
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end
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if ((up_wr_s == 1'b1) && (up_addr[3:0] == 4'h4))
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begin
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control_r <= up_wdata;
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end
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if ((up_wr_s == 1'b1) && (up_addr[3:0] == 4'h5))
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begin
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reference_speed_r <= up_wdata;
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end
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if ((up_wr_s == 1'b1) && (up_addr[3:0] == 4'h6))
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begin
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kp_r <= up_wdata;
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end
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if ((up_wr_s == 1'b1) && (up_addr[3:0] == 4'h7))
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begin
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ki_r <= up_wdata;
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end
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if ((up_wr_s == 1'b1) && (up_addr[3:0] == 4'h8))
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begin
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kd_r <= up_wdata;
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end
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if ((up_wr_s == 1'b1) && (up_addr[3:0] == 4'h9))
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begin
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kp1_r <= up_wdata;
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end
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if ((up_wr_s == 1'b1) && (up_addr[3:0] == 4'ha))
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begin
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ki1_r <= up_wdata;
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end
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if ((up_wr_s == 1'b1) && (up_addr[3:0] == 4'hb))
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begin
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kd1_r <= up_wdata;
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end
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if ((up_wr_s == 1'b1) && (up_addr[3:0] == 4'hc))
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begin
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pwm_open_r <= up_wdata;
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end
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if ((up_wr_s == 1'b1) && (up_addr[3:0] == 4'hd))
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begin
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pwm_break_r <= up_wdata;
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end
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if ((up_wr_s == 1'b1) && (up_addr[3:0] == 4'he))
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begin
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status_r <= up_wdata;
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end
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end
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end
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// processor read interface
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always @(negedge up_rstn or posedge up_clk)
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begin
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if (up_rstn == 0) begin
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up_ack <= 'd0;
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up_rdata <= 'd0;
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end
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else
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begin
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up_ack <= up_sel_s;
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if (up_sel_s == 1'b1) begin
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case (up_addr[3:0])
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4'h3: up_rdata <= reserved_r1;
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4'h4: up_rdata <= control_r;
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4'h5: up_rdata <= reference_speed_r;
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4'h6: up_rdata <= kp_r;
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4'h7: up_rdata <= ki_r;
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4'h8: up_rdata <= kd_r;
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4'h9: up_rdata <= kp1_r;
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4'ha: up_rdata <= ki1_r;
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4'hb: up_rdata <= kd1_r;
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4'hc: up_rdata <= pwm_open_r;
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4'hd: up_rdata <= pwm_break_r;
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4'he: up_rdata <= status_r;
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4'hf: up_rdata <= err_i;
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default: up_rdata <= 0;
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endcase
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end
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else
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begin
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up_rdata <= 32'd0;
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end
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end
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end
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endmodule
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