Istvan Csomortani af5c71a9b2 axi|util_adxcvr: Delete reset interface inference for PLL resets ... The Xilinx's reset interface expect that every reset have an associated interface and clock signal. The tool will try to find its clock and interface, and automatically associated clock signal to it. The PLL resets are individual asynchronous resets. To simplify the design and avoid invalid critical warnings all the reset interface inference for the PLL resets were removed.		2018-08-23 18:41:48 +03:00
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axi_adcfifo	ad_mem_asym: Improve the implementation of the asymmetric RAM	2018-08-06 17:29:05 +03:00
axi_adxcvr	axi|util_adxcvr: Delete reset interface inference for PLL resets	2018-08-23 18:41:48 +03:00
axi_dacfifo	ad_mem_asym: Improve the implementation of the asymmetric RAM	2018-08-06 17:29:05 +03:00
axi_xcvrlb	Move Altera IP core dependency tracking to library Makefiles	2018-04-11 15:09:54 +03:00
common	ad_rst: All the synchronization registers have to have ASYNC_REG TRUE	2018-08-14 17:54:14 +03:00
util_adxcvr	axi|util_adxcvr: Delete reset interface inference for PLL resets	2018-08-23 18:41:48 +03:00