136 lines
4.4 KiB
Verilog
136 lines
4.4 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2015(c) Analog Devices, Inc.
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//
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without modification,
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// are permitted provided that the following conditions are met:
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// - Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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// - Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in
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// the documentation and/or other materials provided with the
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// distribution.
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// - Neither the name of Analog Devices, Inc. nor the names of its
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// contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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// - The use of this software may or may not infringe the patent rights
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// of one or more patent holders. This license does not release you
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// from the requirement that you obtain separate licenses from these
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// patent holders to use this software.
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// - Use of the software either in source or binary form, must be run
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// on or directly connected to an Analog Devices Inc. component.
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//
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// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
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// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
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// PARTICULAR PURPOSE ARE DISCLAIMED.
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//
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// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
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// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
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// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/1ps
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module axi_ad9361_tdd_if(
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// clock
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clk,
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rst,
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// control signals from the tdd control
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tdd_rx_vco_en,
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tdd_tx_vco_en,
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tdd_rx_rf_en,
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tdd_tx_rf_en,
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// device interface
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ad9361_txnrx,
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ad9361_enable,
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// interface status
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ad9361_tdd_status
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);
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// parameters
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parameter MODE_OF_ENABLE = 0;
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localparam PULSE_MODE = 0;
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localparam LEVEL_MODE = 1;
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// clock
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input clk;
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input rst;
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// control signals from the tdd control
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input tdd_rx_vco_en;
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input tdd_tx_vco_en;
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input tdd_rx_rf_en;
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input tdd_tx_rf_en;
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// device interface
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output ad9361_txnrx;
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output ad9361_enable;
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// interface status
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output [ 7:0] ad9361_tdd_status;
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// internal registers
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reg tdd_rx_rf_en_d = 1'b0;
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reg tdd_tx_rf_en_d = 1'b0;
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reg tdd_vco_overlap = 1'b0;
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reg tdd_rf_overlap = 1'b0;
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wire ad9361_txnrx_s;
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wire ad9361_enable_s;
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// just one VCO can be enabled at a time
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assign ad9361_txnrx_s = tdd_tx_vco_en;
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always @(posedge clk) begin
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tdd_rx_rf_en_d <= tdd_rx_rf_en;
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tdd_tx_rf_en_d <= tdd_tx_rf_en;
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end
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assign ad9361_enable_s = (MODE_OF_ENABLE == PULSE_MODE) ?
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((~tdd_rx_rf_en_d & tdd_rx_rf_en) | (tdd_rx_rf_en_d & ~tdd_rx_rf_en) |
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(~tdd_tx_rf_en_d & tdd_tx_rf_en) | (tdd_tx_rf_en_d & ~tdd_tx_rf_en)) :
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(tdd_rx_rf_en | tdd_tx_rf_en);
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always @(posedge clk) begin
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if(rst == 1'b1) begin
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tdd_vco_overlap <= 1'b0;
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tdd_rf_overlap <= 1'b0;
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end else begin
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tdd_vco_overlap <= tdd_rx_vco_en & tdd_tx_vco_en;
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tdd_rf_overlap <= tdd_rx_rf_en & tdd_tx_rf_en;
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end
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end
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assign ad9361_tdd_status = {6'b0, tdd_rf_overlap, tdd_vco_overlap};
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assign ad9361_txnrx = ad9361_txnrx_s;
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assign ad9361_enable = ad9361_enable_s;
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endmodule
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