Lars-Peter Clausen 7a53b99b8b daq2: zc706: Increase DAC FIFO size ... Currently the DAC FIFO size for the ZC706 DAQ2 project is 16kB. This is quite a limiting size for practical applications. Increase the size to 1MB to allow loading larger waveforms. In this configuration the DAC FIFO will use half of the available BRAM cells in the FPGA. This still leaves quite a few BRAMs available for user application logic added to the design. If a user design should run out of BRAMs nevertheless they can reduce the FIFO size, if not required by the application, to free up some cells. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>		2017-04-28 12:29:01 +02:00
..
a10gx	Makefiles: Change MMU enabling parameter for altera designs from MMU to NIOS2_MMU	2017-04-18 10:57:16 +03:00
common	all: Update verilog files to verilog-2001	2017-04-13 11:59:55 +03:00
kc705	all: Update verilog files to verilog-2001	2017-04-13 11:59:55 +03:00
kcu105	daq2: Fix typo	2017-04-24 15:44:45 +03:00
vc707	all: Update verilog files to verilog-2001	2017-04-13 11:59:55 +03:00
zc706	daq2: zc706: Increase DAC FIFO size	2017-04-28 12:29:01 +02:00
zcu102	daq2: Fix typo	2017-04-24 15:44:45 +03:00
Makefile	hdlmake- updates	2016-09-30 13:20:22 -04:00