f0655e63a6
The PLL frequency must be half of the lane rate and the core clock rate must be lane rate divided by 40. There is no other option, otherwise things wont work. Instead of having to manually specify PLL and core clock frequency derive them in the transceiver script. This reduces the risk of accidental misconfiguration. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> |
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| .. | ||
| a10gx | ||
| common | ||
| cpld | ||
| zc706 | ||
| Makefile | ||