Lars-Peter Clausen ec8db3ee5b util_dacfifo: Reduce logic on high fan-out dma_wren_s signal ... The DMAC implementation guarantees that the expression `dma_valid & dma_xfer_req` is always identical to just dma_valid. When generating the util_dacfifo dma_wren_s signal the optimizer doesn't know of this though and hence will route both signals into the LUT that drives the write enable for the BRAMs. Simplify the expression by removing dma_xfer_req from it. Considering this can be a fairly high fan-out net and is typically the bottleneck for the util_dacfifo timing this helps to improve the timing. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>		2018-06-11 09:50:43 +02:00
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Makefile	Move Altera IP core dependency tracking to library Makefiles	2018-04-11 15:09:54 +03:00
util_dacfifo.v	util_dacfifo: Reduce logic on high fan-out dma_wren_s signal	2018-06-11 09:50:43 +02:00
util_dacfifo_constr.sdc	util_dacfifo/constraints- false paths for bypass	2017-03-06 10:33:07 -05:00
util_dacfifo_constr.xdc	util_dacfifo: Define constraints for bypass	2017-03-07 16:14:46 +02:00
util_dacfifo_hw.tcl	util_dacfifo: Integrate grey coder/decoder module	2017-10-05 12:25:50 +01:00
util_dacfifo_ip.tcl	util_dacfifo: Infer clock and reset signals	2018-04-11 15:09:54 +03:00