409 lines
14 KiB
Verilog
409 lines
14 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2011(c) Analog Devices, Inc.
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//
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without modification,
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// are permitted provided that the following conditions are met:
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// - Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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// - Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in
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// the documentation and/or other materials provided with the
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// distribution.
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// - Neither the name of Analog Devices, Inc. nor the names of its
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// contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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// - The use of this software may or may not infringe the patent rights
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// of one or more patent holders. This license does not release you
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// from the requirement that you obtain separate licenses from these
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// patent holders to use this software.
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// - Use of the software either in source or binary form, must be run
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// on or directly connected to an Analog Devices Inc. component.
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//
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// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
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// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
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// PARTICULAR PURPOSE ARE DISCLAIMED.
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//
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// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
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// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
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// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module util_rfifo (
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// d-in interface
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din_rstn,
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din_clk,
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din_enable_0,
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din_valid_0,
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din_data_0,
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din_enable_1,
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din_valid_1,
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din_data_1,
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din_enable_2,
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din_valid_2,
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din_data_2,
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din_enable_3,
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din_valid_3,
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din_data_3,
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din_enable_4,
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din_valid_4,
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din_data_4,
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din_enable_5,
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din_valid_5,
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din_data_5,
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din_enable_6,
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din_valid_6,
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din_data_6,
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din_enable_7,
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din_valid_7,
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din_data_7,
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din_unf,
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// d-out interface
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dout_rst,
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dout_clk,
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dout_enable_0,
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dout_valid_0,
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dout_data_0,
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dout_enable_1,
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dout_valid_1,
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dout_data_1,
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dout_enable_2,
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dout_valid_2,
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dout_data_2,
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dout_enable_3,
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dout_valid_3,
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dout_data_3,
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dout_enable_4,
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dout_valid_4,
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dout_data_4,
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dout_enable_5,
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dout_valid_5,
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dout_data_5,
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dout_enable_6,
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dout_valid_6,
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dout_data_6,
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dout_enable_7,
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dout_valid_7,
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dout_data_7,
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dout_unf);
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// parameters
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parameter NUM_OF_CHANNELS = 4;
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parameter DIN_DATA_WIDTH = 32;
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parameter DOUT_DATA_WIDTH = 64;
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parameter DIN_ADDRESS_WIDTH = 8;
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localparam M_MEM_RATIO = DOUT_DATA_WIDTH/DIN_DATA_WIDTH;
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localparam ADDRESS_WIDTH = (DIN_ADDRESS_WIDTH > 5) ? DIN_ADDRESS_WIDTH : 5;
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localparam DATA_WIDTH = DOUT_DATA_WIDTH * NUM_OF_CHANNELS;
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localparam T_DIN_DATA_WIDTH = DIN_DATA_WIDTH * 8;
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localparam T_DOUT_DATA_WIDTH = DOUT_DATA_WIDTH * 8;
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// d-in interface
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input din_rstn;
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input din_clk;
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output din_enable_0;
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output din_valid_0;
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input [DIN_DATA_WIDTH-1:0] din_data_0;
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output din_enable_1;
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output din_valid_1;
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input [DIN_DATA_WIDTH-1:0] din_data_1;
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output din_enable_2;
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output din_valid_2;
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input [DIN_DATA_WIDTH-1:0] din_data_2;
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output din_enable_3;
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output din_valid_3;
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input [DIN_DATA_WIDTH-1:0] din_data_3;
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output din_enable_4;
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output din_valid_4;
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input [DIN_DATA_WIDTH-1:0] din_data_4;
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output din_enable_5;
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output din_valid_5;
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input [DIN_DATA_WIDTH-1:0] din_data_5;
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output din_enable_6;
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output din_valid_6;
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input [DIN_DATA_WIDTH-1:0] din_data_6;
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output din_enable_7;
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output din_valid_7;
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input [DIN_DATA_WIDTH-1:0] din_data_7;
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input din_unf;
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// dout interface
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input dout_rst;
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input dout_clk;
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input dout_enable_0;
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input dout_valid_0;
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output [DOUT_DATA_WIDTH-1:0] dout_data_0;
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input dout_enable_1;
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input dout_valid_1;
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output [DOUT_DATA_WIDTH-1:0] dout_data_1;
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input dout_enable_2;
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input dout_valid_2;
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output [DOUT_DATA_WIDTH-1:0] dout_data_2;
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input dout_enable_3;
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input dout_valid_3;
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output [DOUT_DATA_WIDTH-1:0] dout_data_3;
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input dout_enable_4;
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input dout_valid_4;
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output [DOUT_DATA_WIDTH-1:0] dout_data_4;
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input dout_enable_5;
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input dout_valid_5;
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output [DOUT_DATA_WIDTH-1:0] dout_data_5;
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input dout_enable_6;
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input dout_valid_6;
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output [DOUT_DATA_WIDTH-1:0] dout_data_6;
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input dout_enable_7;
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input dout_valid_7;
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output [DOUT_DATA_WIDTH-1:0] dout_data_7;
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output dout_unf;
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// internal registers
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reg [(DATA_WIDTH-1):0] din_wdata = 'd0;
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reg [(ADDRESS_WIDTH-1):0] din_waddr = 'hc;
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reg din_wr = 'd0;
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reg din_valid = 'd0;
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reg [ 6:0] din_req_cnt = 'd0;
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reg [ 7:0] din_enable_m1 = 'd0;
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reg [ 7:0] din_enable = 'd0;
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reg din_req_t_m1 = 'd0;
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reg din_req_t_m2 = 'd0;
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reg din_req_t_m3 = 'd0;
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reg din_req = 'd0;
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reg [(ADDRESS_WIDTH-4):0] din_rinit = 'd0;
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reg din_unf_d = 'd0;
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reg [(T_DOUT_DATA_WIDTH+1):0] dout_data = 'd0;
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reg [(DATA_WIDTH-1):0] dout_rdata = 'd0;
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reg [ 7:0] dout_enable = 'd0;
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reg dout_req_t = 'd0;
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reg [(ADDRESS_WIDTH-4):0] dout_rinit = 'd0;
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reg [(ADDRESS_WIDTH-1):0] dout_raddr = 'd0;
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reg dout_unf_m1 = 'd0;
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reg dout_unf = 'd0;
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// internal signals
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wire [(T_DIN_DATA_WIDTH-1):0] din_data_s;
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wire din_req_s;
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wire [ 7:0] dout_enable_s;
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wire [ 7:0] dout_valid_s;
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wire [(T_DOUT_DATA_WIDTH+1):0] dout_data_s;
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wire [(DATA_WIDTH-1):0] dout_rdata_s;
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// variables
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genvar n;
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// enables & valids
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assign din_enable_7 = din_enable[7];
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assign din_enable_6 = din_enable[6];
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assign din_enable_5 = din_enable[5];
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assign din_enable_4 = din_enable[4];
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assign din_enable_3 = din_enable[3];
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assign din_enable_2 = din_enable[2];
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assign din_enable_1 = din_enable[1];
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assign din_enable_0 = din_enable[0];
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assign din_valid_7 = din_valid;
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assign din_valid_6 = din_valid;
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assign din_valid_5 = din_valid;
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assign din_valid_4 = din_valid;
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assign din_valid_3 = din_valid;
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assign din_valid_2 = din_valid;
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assign din_valid_1 = din_valid;
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assign din_valid_0 = din_valid;
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assign din_data_s = { din_data_7, din_data_6, din_data_5, din_data_4,
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din_data_3, din_data_2, din_data_1, din_data_0};
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// simple data transfer-- no ovf/unf handling- read-bw > write-bw
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// dout_width >= din_width only
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generate
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for (n = 0; n < NUM_OF_CHANNELS; n = n + 1) begin: g_in
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if (M_MEM_RATIO == 1) begin
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always @(posedge din_clk) begin
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if (din_valid == 1'b1) begin
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din_wdata[((DOUT_DATA_WIDTH*(n+1))-1):(DOUT_DATA_WIDTH*n)] <=
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din_data_s[((DIN_DATA_WIDTH*(n+1))-1):(DIN_DATA_WIDTH*n)];
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end
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end
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end else begin
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always @(posedge din_clk) begin
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if (din_valid == 1'b1) begin
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din_wdata[((DOUT_DATA_WIDTH*(n+1))-1):(DOUT_DATA_WIDTH*n)] <=
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{din_data_s[((DIN_DATA_WIDTH*(n+1))-1):(DIN_DATA_WIDTH*n)],
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din_wdata[((DOUT_DATA_WIDTH*(n+1))-1):(DIN_DATA_WIDTH+(DOUT_DATA_WIDTH*n))]};
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end
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end
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end
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end
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endgenerate
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always @(posedge din_clk or negedge din_rstn) begin
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if (din_rstn == 1'b0) begin
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din_waddr <= 'hc;
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din_wr <= 1'd0;
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end else begin
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if (din_req == 1'b1) begin
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din_waddr <= {din_rinit, 3'd0};
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end else if (din_wr == 1'b1) begin
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din_waddr <= din_waddr + 1'b1;
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end
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case (M_MEM_RATIO)
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8: din_wr <= din_req_cnt[6] & din_req_cnt[2] & din_req_cnt[1] & din_req_cnt[0];
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4: din_wr <= din_req_cnt[6] & din_req_cnt[1] & din_req_cnt[0];
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2: din_wr <= din_req_cnt[6] & din_req_cnt[0];
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default: din_wr <= din_req_cnt[6];
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endcase
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end
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end
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always @(posedge din_clk or negedge din_rstn) begin
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if (din_rstn == 1'b0) begin
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din_valid <= 'd0;
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din_req_cnt <= 'd0;
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end else begin
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din_valid <= din_req_cnt[6];
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if (din_req_s == 1'b1) begin
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case (M_MEM_RATIO)
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8: din_req_cnt <= 7'h40;
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4: din_req_cnt <= 7'h60;
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2: din_req_cnt <= 7'h70;
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default: din_req_cnt <= 7'h78;
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endcase
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end else if (din_req_cnt[6] == 1'b1) begin
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din_req_cnt <= din_req_cnt + 1'b1;
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end
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end
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end
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assign din_req_s = din_req_t_m3 ^ din_req_t_m2;
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always @(posedge din_clk or negedge din_rstn) begin
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if (din_rstn == 1'b0) begin
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din_enable_m1 <= 'd0;
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din_enable <= 'd0;
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din_req_t_m1 <= 'd0;
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din_req_t_m2 <= 'd0;
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din_req_t_m3 <= 'd0;
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din_req <= 'd0;
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din_rinit <= 'd0;
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din_unf_d <= 'd0;
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end else begin
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din_enable_m1 <= dout_enable;
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din_enable <= din_enable_m1;
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din_req_t_m1 <= dout_req_t;
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din_req_t_m2 <= din_req_t_m1;
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din_req_t_m3 <= din_req_t_m2;
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din_req <= din_req_s;
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if (din_req_s == 1'b1) begin
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din_rinit <= dout_rinit;
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end
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din_unf_d <= din_unf;
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end
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end
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// read interface (bus expansion and/or clock conversion)
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assign dout_enable_s = { dout_enable_7, dout_enable_6, dout_enable_5, dout_enable_4,
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dout_enable_3, dout_enable_2, dout_enable_1, dout_enable_0};
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assign dout_valid_s = { dout_valid_7, dout_valid_6, dout_valid_5, dout_valid_4,
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dout_valid_3, dout_valid_2, dout_valid_1, dout_valid_0};
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generate
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if (NUM_OF_CHANNELS >= 8) begin
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assign dout_data_s = dout_rdata;
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end else begin
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assign dout_data_s[(T_DOUT_DATA_WIDTH+1):DATA_WIDTH] = 'd0;
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assign dout_data_s[(DATA_WIDTH-1):0] = dout_rdata;
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end
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endgenerate
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assign dout_data_7 = dout_data[((DOUT_DATA_WIDTH*8)-1):(DOUT_DATA_WIDTH*7)];
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assign dout_data_6 = dout_data[((DOUT_DATA_WIDTH*7)-1):(DOUT_DATA_WIDTH*6)];
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assign dout_data_5 = dout_data[((DOUT_DATA_WIDTH*6)-1):(DOUT_DATA_WIDTH*5)];
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assign dout_data_4 = dout_data[((DOUT_DATA_WIDTH*5)-1):(DOUT_DATA_WIDTH*4)];
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assign dout_data_3 = dout_data[((DOUT_DATA_WIDTH*4)-1):(DOUT_DATA_WIDTH*3)];
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assign dout_data_2 = dout_data[((DOUT_DATA_WIDTH*3)-1):(DOUT_DATA_WIDTH*2)];
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assign dout_data_1 = dout_data[((DOUT_DATA_WIDTH*2)-1):(DOUT_DATA_WIDTH*1)];
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assign dout_data_0 = dout_data[((DOUT_DATA_WIDTH*1)-1):(DOUT_DATA_WIDTH*0)];
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generate
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for (n = 0; n < NUM_OF_CHANNELS; n = n + 1) begin: g_out
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always @(posedge dout_clk) begin
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if (dout_rst == 1'b1) begin
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dout_data[((DOUT_DATA_WIDTH*(n+1))-1):(DOUT_DATA_WIDTH*n)] <= 'd0;
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end else if (dout_valid_s[n] == 1'b1) begin
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dout_data[((DOUT_DATA_WIDTH*(n+1))-1):(DOUT_DATA_WIDTH*n)] <=
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dout_data_s[((DOUT_DATA_WIDTH*(n+1))-1):(DOUT_DATA_WIDTH*n)];
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end
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end
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end
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endgenerate
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always @(posedge dout_clk) begin
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dout_rdata <= dout_rdata_s;
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end
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always @(posedge dout_clk) begin
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if (dout_rst == 1'b1) begin
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dout_enable <= 'd0;
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dout_req_t <= 'd0;
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dout_rinit <= 'd0;
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dout_raddr <= 'd0;
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end else begin
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dout_enable <= dout_enable_s;
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if (dout_valid_s[0] == 1'b1) begin
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if (dout_raddr[2:0] == 3'd7) begin
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dout_req_t <= ~dout_req_t;
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dout_rinit <= dout_raddr[(ADDRESS_WIDTH-1):3] + 2'd2;
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end
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dout_raddr <= dout_raddr + 1'b1;
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end
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end
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end
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always @(posedge dout_clk) begin
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if (dout_rst == 1'b1) begin
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dout_unf_m1 <= 'd0;
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dout_unf <= 'd0;
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end else begin
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dout_unf_m1 <= din_unf_d;
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dout_unf <= dout_unf_m1;
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end
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end
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// instantiations
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ad_mem #(.ADDRESS_WIDTH(ADDRESS_WIDTH), .DATA_WIDTH(DATA_WIDTH)) i_mem (
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.clka (din_clk),
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.wea (din_wr),
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.addra (din_waddr),
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.dina (din_wdata),
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.clkb (dout_clk),
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.addrb (dout_raddr),
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.doutb (dout_rdata_s));
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endmodule
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// ***************************************************************************
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// ***************************************************************************
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