103 lines
3.0 KiB
Verilog
103 lines
3.0 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2018 (c) Analog Devices, Inc. All rights reserved.
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//
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// Each core or library found in this collection may have its own licensing terms.
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// The user should keep this in in mind while exploring these cores.
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//
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// Redistribution and use in source and binary forms,
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// with or without modification of this file, are permitted under the terms of either
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// (at the option of the user):
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//
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// 1. The GNU General Public License version 2 as published by the
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// Free Software Foundation, which can be found in the top level directory, or at:
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// https://www.gnu.org/licenses/old-licenses/gpl-2.0.en.html
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//
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// OR
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//
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// 2. An ADI specific BSD license as noted in the top level directory, or on-line at:
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// https://github.com/analogdevicesinc/hdl/blob/dev/LICENSE
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//
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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// Generic parallel PN generator
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module ad_pngen #(
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// PN7 x^7 + x^6 + 1
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parameter POL_MASK = 32'b0000_0000_0000_0000_0000_0000_1100_0000,
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parameter POL_W = 7,
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// Number of output bits at every clock cycle
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parameter DW = 16
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) (
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input clk,
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input reset,
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input clk_en,
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// Output stream
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output [DW-1:0] pn_data_out, // MSB has the oldest value,
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// LSB has the latest value
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// Input stream to synchronize to (Optional)
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input pn_init,
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input [DW-1:0] pn_data_in
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);
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/* We need at least enough bits to store the PN state */
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localparam PN_W = DW > POL_W ? DW : POL_W;
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reg [PN_W-1:0] pn_state = {PN_W{1'b1}};
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wire [DW-1:0] pn;
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wire [DW+POL_W-1:0] pn_full_state;
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wire [PN_W-1:0] pn_reset;
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wire [PN_W-1:0] pn_state_;
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wire [PN_W-1:0] pn_init_data;
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// pn init data selection
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generate if (PN_W > DW) begin
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reg [PN_W-DW-1:0] pn_data_in_d = 'd0;
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always @(posedge clk) begin
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pn_data_in_d <= {pn_data_in_d, pn_data_in};
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end
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assign pn_init_data = {pn_data_in_d, pn_data_in};
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end else begin
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assign pn_init_data = pn_data_in;
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end
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endgenerate
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// PRBS logic
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assign pn_state_ = pn_init ? pn_init_data : pn_state;
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generate
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genvar i;
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for (i = 0; i < DW; i = i + 1) begin: pn_loop
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assign pn[i] = ^(pn_full_state[i +: POL_W+1] & POL_MASK);
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end
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endgenerate
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assign pn_full_state = {pn_state_[POL_W-1 : 0],pn};
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// Reset value logic
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assign pn_reset[PN_W-1 -: POL_W] = {POL_W{1'b1}};
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generate
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genvar j;
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for (j = 0; j < PN_W-POL_W; j = j + 1) begin: pn_reset_loop
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assign pn_reset[j] = ^(pn_reset[j +: POL_W+1] & POL_MASK);
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end
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endgenerate
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always @(posedge clk) begin
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if (reset == 1'b1) begin
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pn_state <= pn_reset;
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end else if (clk_en) begin
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pn_state <= pn_full_state[PN_W-1 : 0];
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end
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end
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assign pn_data_out = pn_state[PN_W-1 -: DW];
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endmodule
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