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a5gt
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fmcjesdadc1/a5gt- hard placement of ddr hr/qr registers
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2017-02-17 15:21:33 -05:00 |
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a5gte
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a5gte: Fixed timing violations
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2016-12-13 10:30:24 +02:00 |
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a5soc
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common/a5soc- device can not run at 100M cpu clock
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2016-11-08 15:19:23 -05:00 |
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a10gx
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adrv9371x- altera updates
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2016-10-27 09:25:00 -04:00 |
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a10soc
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a10soc - remove default assignments
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2016-11-04 15:01:19 -04:00 |
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ac701
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common/ac701: Connect axi_ddr_cntrl/device_temp_i to GND
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2016-12-09 13:54:39 +02:00 |
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altera
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projects/altera- qii_auto_pack option
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2016-12-22 14:14:21 -05:00 |
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c5soc
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arradio: Revert tcl related changes, to fix DDR Bandwidth related issue
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2017-07-19 15:17:55 +03:00 |
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kc705
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kc705: Fix ethernet address span
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2017-06-30 14:20:39 +03:00 |
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kcu105
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kcu105- added missing ethernet configurations
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2017-01-23 10:14:09 -05:00 |
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microzed
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common: microzed: Add clock, reset and interrupt support
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2016-01-13 20:32:26 +01:00 |
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mitx045
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version_upgrade: Update ac701, mitx045 and zed common design to Vivado 2016.2
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2016-08-29 09:50:46 +03:00 |
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vc707
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common/vc707- 2016.2 version
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2016-08-17 10:36:19 -04:00 |
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xilinx
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dmafifo-split to adc/dac
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2016-08-16 12:54:39 -04:00 |
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zc702
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version_upgrade: Common ZC702 get an upgrade to 2016.2
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2016-08-26 10:20:04 +03:00 |
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zc706
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axi_dacfifo: Redesign the bypass functionality
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2017-04-03 10:37:08 +03:00 |
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zcu102
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zcu102/*- actual clock == desired clock
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2017-02-06 12:53:47 -05:00 |
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zed
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version_upgrade: Update ac701, mitx045 and zed common design to Vivado 2016.2
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2016-08-29 09:50:46 +03:00 |
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Makefile
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Makefiles: Updated Makefiles
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2015-10-23 10:44:27 +03:00 |
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