280 lines
7.8 KiB
Verilog
280 lines
7.8 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2011(c) Analog Devices, Inc.
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//
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without modification,
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// are permitted provided that the following conditions are met:
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// - Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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// - Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in
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// the documentation and/or other materials provided with the
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// distribution.
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// - Neither the name of Analog Devices, Inc. nor the names of its
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// contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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// - The use of this software may or may not infringe the patent rights
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// of one or more patent holders. This license does not release you
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// from the requirement that you obtain separate licenses from these
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// patent holders to use this software.
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// - Use of the software either in source or binary form, must be run
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// on or directly connected to an Analog Devices Inc. component.
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//
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// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
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// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
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// PARTICULAR PURPOSE ARE DISCLAIMED.
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//
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// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
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// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
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// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module system_top (
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sys_rst,
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sys_clk_p,
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sys_clk_n,
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uart_sin,
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uart_sout,
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ddr3_1_n,
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ddr3_1_p,
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ddr3_reset_n,
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ddr3_addr,
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ddr3_ba,
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ddr3_cas_n,
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ddr3_ras_n,
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ddr3_we_n,
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ddr3_ck_n,
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ddr3_ck_p,
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ddr3_cke,
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ddr3_cs_n,
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ddr3_dm,
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ddr3_dq,
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ddr3_dqs_n,
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ddr3_dqs_p,
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ddr3_odt,
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mdio_mdc,
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mdio_mdio,
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mii_rst_n,
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mii_col,
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mii_crs,
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mii_rx_clk,
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mii_rx_er,
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mii_rx_dv,
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mii_rxd,
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mii_tx_clk,
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mii_tx_en,
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mii_txd,
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linear_flash_addr,
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linear_flash_adv_ldn,
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linear_flash_ce_n,
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linear_flash_dq_io,
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linear_flash_oen,
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linear_flash_wen,
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fan_pwm,
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gpio_lcd,
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gpio_bd,
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iic_rstn,
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iic_scl,
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iic_sda,
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adc_clk_in_n,
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adc_clk_in_p,
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adc_data_in_n,
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adc_data_in_p,
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adc_data_or_n,
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adc_data_or_p,
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spi_clk,
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spi_csn_adc,
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spi_csn_clk,
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spi_sdio
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);
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input sys_rst;
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input sys_clk_p;
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input sys_clk_n;
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input uart_sin;
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output uart_sout;
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output [ 2:0] ddr3_1_n;
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output [ 1:0] ddr3_1_p;
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output ddr3_reset_n;
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output [13:0] ddr3_addr;
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output [ 2:0] ddr3_ba;
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output ddr3_cas_n;
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output ddr3_ras_n;
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output ddr3_we_n;
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output [ 0:0] ddr3_ck_n;
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output [ 0:0] ddr3_ck_p;
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output [ 0:0] ddr3_cke;
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output [ 0:0] ddr3_cs_n;
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output [ 7:0] ddr3_dm;
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inout [63:0] ddr3_dq;
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inout [ 7:0] ddr3_dqs_n;
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inout [ 7:0] ddr3_dqs_p;
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output [ 0:0] ddr3_odt;
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output mdio_mdc;
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inout mdio_mdio;
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output mii_rst_n;
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input mii_col;
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input mii_crs;
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input mii_rx_clk;
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input mii_rx_er;
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input mii_rx_dv;
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input [ 3:0] mii_rxd;
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input mii_tx_clk;
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output mii_tx_en;
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output [ 3:0] mii_txd;
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output [26:1] linear_flash_addr;
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output linear_flash_adv_ldn;
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output linear_flash_ce_n;
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inout [15:0] linear_flash_dq_io;
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output linear_flash_oen;
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output linear_flash_wen;
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output fan_pwm;
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inout [ 6:0] gpio_lcd;
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inout [16:0] gpio_bd;
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output iic_rstn;
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inout iic_scl;
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inout iic_sda;
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input adc_clk_in_n;
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input adc_clk_in_p;
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input [ 7:0] adc_data_in_n;
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input [ 7:0] adc_data_in_p;
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input adc_data_or_n;
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input adc_data_or_p;
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output spi_clk;
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output spi_csn_adc;
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output spi_csn_clk;
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inout spi_sdio;
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// internal signals
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wire [ 7:0] spi_csn;
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wire spi_miso;
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wire spi_mosi;
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wire [63:0] gpio_i;
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wire [63:0] gpio_o;
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wire [63:0] gpio_t;
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assign ddr3_1_p = 2'b11;
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assign ddr3_1_n = 3'b000;
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assign fan_pwm = 1'b1;
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assign iic_rstn = 1'b1;
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assign spi_csn_adc = spi_csn[0];
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assign spi_csn_clk = spi_csn[1];
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ad9467_spi i_spi (
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.spi_csn(spi_csn[1:0]),
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.spi_clk(spi_clk),
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.spi_mosi(spi_mosi),
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.spi_miso(spi_miso),
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.spi_sdio(spi_sdio)
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);
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ad_iobuf #(.DATA_WIDTH(17)) i_iobuf_sw_led (
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.dio_t (gpio_t[16:0]),
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.dio_i (gpio_o[16:0]),
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.dio_o (gpio_i[16:0]),
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.dio_p (gpio_bd));
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system_wrapper i_system_wrapper (
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.ddr3_addr (ddr3_addr),
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.ddr3_ba (ddr3_ba),
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.ddr3_cas_n (ddr3_cas_n),
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.ddr3_ck_n (ddr3_ck_n),
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.ddr3_ck_p (ddr3_ck_p),
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.ddr3_cke (ddr3_cke),
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.ddr3_cs_n (ddr3_cs_n),
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.ddr3_dm (ddr3_dm),
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.ddr3_dq (ddr3_dq),
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.ddr3_dqs_n (ddr3_dqs_n),
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.ddr3_dqs_p (ddr3_dqs_p),
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.ddr3_odt (ddr3_odt),
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.ddr3_ras_n (ddr3_ras_n),
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.ddr3_reset_n (ddr3_reset_n),
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.ddr3_we_n (ddr3_we_n),
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.gpio_lcd_tri_io (gpio_lcd),
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.gpio0_o (gpio_o[31:0]),
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.gpio0_t (gpio_t[31:0]),
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.gpio0_i (gpio_i[31:0]),
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.gpio1_o (gpio_o[63:32]),
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.gpio1_t (gpio_t[63:32]),
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.gpio1_i (gpio_i[63:32]),
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.iic_main_scl_io (iic_scl),
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.iic_main_sda_io (iic_sda),
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.mb_intr_02 (1'b0),
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.mb_intr_03 (1'b0),
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.mb_intr_06 (1'b0),
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.mb_intr_07 (1'b0),
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.mb_intr_08 (1'b0),
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.mb_intr_13 (1'b0),
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.mb_intr_14 (1'b0),
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.mb_intr_15 (1'b0),
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.mdio_mdc (mdio_mdc),
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.mdio_mdio_io (mdio_mdio),
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.mii_col (mii_col),
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.mii_crs (mii_crs),
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.mii_rst_n (mii_rst_n),
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.mii_rx_clk (mii_rx_clk),
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.mii_rx_dv (mii_rx_dv),
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.mii_rx_er (mii_rx_er),
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.mii_rxd (mii_rxd),
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.mii_tx_clk (mii_tx_clk),
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.mii_tx_en (mii_tx_en),
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.mii_txd (mii_txd),
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.linear_flash_addr (linear_flash_addr),
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.linear_flash_adv_ldn (linear_flash_adv_ldn),
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.linear_flash_ce_n (linear_flash_ce_n),
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.linear_flash_dq_io (linear_flash_dq_io),
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.linear_flash_oen (linear_flash_oen),
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.linear_flash_wen (linear_flash_wen),
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.sys_clk_n (sys_clk_n),
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.sys_clk_p (sys_clk_p),
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.sys_rst (sys_rst),
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.uart_sin (uart_sin),
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.uart_sout (uart_sout),
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.adc_clk_in_n (adc_clk_in_n),
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.adc_clk_in_p (adc_clk_in_p),
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.adc_data_in_n (adc_data_in_n),
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.adc_data_in_p (adc_data_in_p),
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.adc_data_or_n (adc_data_or_n),
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.adc_data_or_p (adc_data_or_p),
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.spi_clk_i (1'b0),
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.spi_clk_o (spi_clk),
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.spi_csn_i (1'b1),
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.spi_csn_o (spi_csn),
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.spi_sdi_i (spi_miso),
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.spi_sdo_i (1'b0),
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.spi_sdo_o (spi_mosi));
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endmodule
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// ***************************************************************************
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// ***************************************************************************
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