123 lines
4.4 KiB
Tcl
123 lines
4.4 KiB
Tcl
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package require qsys
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source ../scripts/adi_env.tcl
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source ../scripts/adi_ip_alt.tcl
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ad_ip_create axi_ad9684 {AXI AD9684 Interface} axi_ad9684_elab
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ad_ip_files axi_ad9684 [list \
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$ad_hdl_dir/library/common/ad_rst.v \
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$ad_hdl_dir/library/common/ad_datafmt.v \
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$ad_hdl_dir/library/common/ad_pnmon.v \
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$ad_hdl_dir/library/common/up_xfer_status.v \
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$ad_hdl_dir/library/common/up_xfer_cntrl.v \
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$ad_hdl_dir/library/common/up_clock_mon.v \
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$ad_hdl_dir/library/common/up_delay_cntrl.v \
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$ad_hdl_dir/library/common/up_adc_common.v \
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$ad_hdl_dir/library/common/up_adc_channel.v \
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$ad_hdl_dir/library/common/up_axi.v \
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axi_ad9684_pnmon.v \
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axi_ad9684_if.v \
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axi_ad9684_channel.v \
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axi_ad9684.v \
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$ad_hdl_dir/library/altera/common/up_xfer_cntrl_constr.sdc \
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$ad_hdl_dir/library/altera/common/up_xfer_status_constr.sdc \
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$ad_hdl_dir/library/altera/common/up_clock_mon_constr.sdc \
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$ad_hdl_dir/library/altera/common/up_rst_constr.sdc \
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axi_ad9684_constr.sdc] \
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axi_ad9684_fileset
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# parameters
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add_parameter ID INTEGER 0
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set_parameter_property ID DEFAULT_VALUE 0
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set_parameter_property ID DISPLAY_NAME ID
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set_parameter_property ID TYPE INTEGER
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set_parameter_property ID DESCRIPTION "Instance ID"
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set_parameter_property ID UNITS None
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set_parameter_property ID HDL_PARAMETER true
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add_parameter DEVICE_TYPE INTEGER 0
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set_parameter_property DEVICE_TYPE DEFAULT_VALUE 0
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set_parameter_property DEVICE_TYPE DISPLAY_NAME DEVICE_TYPE
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set_parameter_property DEVICE_TYPE TYPE INTEGER
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set_parameter_property DEVICE_TYPE DESCRIPTION "Specify the FPGA device type"
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set_parameter_property DEVICE_TYPE UNITS None
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set_parameter_property DEVICE_TYPE HDL_PARAMETER true
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add_parameter OR_STATUS INTEGER 1
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set_parameter_property OR_STATUS DEFAULT_VALUE 1
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set_parameter_property OR_STATUS DISPLAY_NAME OR_STATUS
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set_parameter_property OR_STATUS TYPE INTEGER
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set_parameter_property OR_STATUS DESCRIPTION "This parameter enables the OVER RANGE line at the physical interface"
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set_parameter_property OR_STATUS UNITS None
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set_parameter_property OR_STATUS HDL_PARAMETER true
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# axi4 slave
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ad_ip_intf_s_axi s_axi_aclk s_axi_aresetn
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# adc device interface
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add_interface device_if conduit end
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set_interface_property device_if associatedClock none
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set_interface_property device_if associatedReset none
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add_interface_port device_if adc_clk_in_p adc_clk_in_p Input 1
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add_interface_port device_if adc_clk_in_n adc_clk_in_n Input 1
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add_interface_port device_if adc_data_in_p adc_data_in_p Input 14
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add_interface_port device_if adc_data_in_n adc_data_in_n Input 14
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# dma interface
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ad_alt_intf clock adc_clk output 1
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ad_alt_intf reset adc_rst output 1 if_adc_clk
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add_interface adc_ch_0 conduit end
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add_interface_port adc_ch_0 adc_valid_0 valid Output 1
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add_interface_port adc_ch_0 adc_enable_0 enable Output 1
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add_interface_port adc_ch_0 adc_data_0 data Output 32
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set_interface_property adc_ch_0 associatedClock if_adc_clk
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set_interface_property adc_ch_0 associatedReset none
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add_interface adc_ch_1 conduit end
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add_interface_port adc_ch_1 adc_valid_1 valid Output 1
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add_interface_port adc_ch_1 adc_enable_1 enable Output 1
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add_interface_port adc_ch_1 adc_data_1 data Output 32
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set_interface_property adc_ch_1 associatedClock if_adc_clk
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set_interface_property adc_ch_1 associatedReset none
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ad_alt_intf signal adc_dovf input 1 ovf
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ad_alt_intf signal adc_dunf input 1 unf
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# SERDES instances and configurations
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add_hdl_instance ad_serdes_clk_core_rx alt_serdes
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set_instance_parameter_value ad_serdes_clk_core_rx {MODE} {CLK}
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set_instance_parameter_value ad_serdes_clk_core_rx {DDR_OR_SDR_N} {1}
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set_instance_parameter_value ad_serdes_clk_core_rx {SERDES_FACTOR} {4}
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set_instance_parameter_value ad_serdes_clk_core_rx {CLKIN_FREQUENCY} {500.0}
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add_hdl_instance ad_serdes_in_core alt_serdes
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set_instance_parameter_value ad_serdes_in_core {MODE} {IN}
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set_instance_parameter_value ad_serdes_in_core {DDR_OR_SDR_N} {1}
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set_instance_parameter_value ad_serdes_in_core {SERDES_FACTOR} {4}
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set_instance_parameter_value ad_serdes_in_core {CLKIN_FREQUENCY} {500.0}
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proc axi_ad9684_elab {} {
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set or_status [get_parameter_value OR_STATUS]
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if {$or_status == 1} {
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add_interface_port device_if adc_data_or_p adc_data_or_p Input 1
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add_interface_port device_if adc_data_or_n adc_data_or_n Input 1
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}
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}
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proc axi_ad9684_fileset { entityName } {
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ad_ip_modfile ad_serdes_in.v ad_serdes_in.v ad_serdes_in_core
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ad_ip_modfile ad_serdes_clk.v ad_serdes_clk.v ad_serdes_clk_core_rx
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}
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