623 lines
22 KiB
Verilog
623 lines
22 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
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//
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// In this HDL repository, there are many different and unique modules, consisting
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// of various HDL (Verilog or VHDL) components. The individual modules are
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// developed independently, and may be accompanied by separate and unique license
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// terms.
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//
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// The user should read each of these license terms, and understand the
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// freedoms and responsibilities that he or she has by using this source/core.
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//
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// This core is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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// A PARTICULAR PURPOSE.
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//
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// Redistribution and use of source or resulting binaries, with or without modification
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// of this file, are permitted under one of the following two license terms:
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//
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// 1. The GNU General Public License version 2 as published by the
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// Free Software Foundation, which can be found in the top level directory
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// of this repository (LICENSE_GPL2), and also online at:
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// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
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//
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// OR
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//
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// 2. An ADI specific BSD license, which can be found in the top level directory
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// of this repository (LICENSE_ADIBSD), and also on-line at:
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// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
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// This will allow to generate bit files and not release the source code,
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// as long as it attaches to an ADI device.
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//
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module axi_ad9739a_channel #(
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parameter CHANNEL_ID = 32'h0,
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parameter DATAPATH_DISABLE = 0) (
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// dac interface
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input dac_div_clk,
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input dac_rst,
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output reg dac_enable,
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output reg [ 15:0] dac_data_00,
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output reg [ 15:0] dac_data_01,
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output reg [ 15:0] dac_data_02,
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output reg [ 15:0] dac_data_03,
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output reg [ 15:0] dac_data_04,
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output reg [ 15:0] dac_data_05,
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output reg [ 15:0] dac_data_06,
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output reg [ 15:0] dac_data_07,
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output reg [ 15:0] dac_data_08,
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output reg [ 15:0] dac_data_09,
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output reg [ 15:0] dac_data_10,
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output reg [ 15:0] dac_data_11,
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output reg [ 15:0] dac_data_12,
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output reg [ 15:0] dac_data_13,
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output reg [ 15:0] dac_data_14,
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output reg [ 15:0] dac_data_15,
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input [255:0] dma_data,
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// processor interface
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input dac_data_sync,
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input dac_dds_format,
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// bus interface
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input up_rstn,
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input up_clk,
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input up_wreq,
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input [ 13:0] up_waddr,
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input [ 31:0] up_wdata,
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output up_wack,
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input up_rreq,
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input [ 13:0] up_raddr,
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output [ 31:0] up_rdata,
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output up_rack);
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// internal registers
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reg [ 15:0] dac_dds_phase_00_0 = 'd0;
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reg [ 15:0] dac_dds_phase_00_1 = 'd0;
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reg [ 15:0] dac_dds_phase_01_0 = 'd0;
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reg [ 15:0] dac_dds_phase_01_1 = 'd0;
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reg [ 15:0] dac_dds_phase_02_0 = 'd0;
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reg [ 15:0] dac_dds_phase_02_1 = 'd0;
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reg [ 15:0] dac_dds_phase_03_0 = 'd0;
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reg [ 15:0] dac_dds_phase_03_1 = 'd0;
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reg [ 15:0] dac_dds_phase_04_0 = 'd0;
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reg [ 15:0] dac_dds_phase_04_1 = 'd0;
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reg [ 15:0] dac_dds_phase_05_0 = 'd0;
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reg [ 15:0] dac_dds_phase_05_1 = 'd0;
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reg [ 15:0] dac_dds_phase_06_0 = 'd0;
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reg [ 15:0] dac_dds_phase_06_1 = 'd0;
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reg [ 15:0] dac_dds_phase_07_0 = 'd0;
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reg [ 15:0] dac_dds_phase_07_1 = 'd0;
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reg [ 15:0] dac_dds_phase_08_0 = 'd0;
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reg [ 15:0] dac_dds_phase_08_1 = 'd0;
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reg [ 15:0] dac_dds_phase_09_0 = 'd0;
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reg [ 15:0] dac_dds_phase_09_1 = 'd0;
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reg [ 15:0] dac_dds_phase_10_0 = 'd0;
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reg [ 15:0] dac_dds_phase_10_1 = 'd0;
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reg [ 15:0] dac_dds_phase_11_0 = 'd0;
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reg [ 15:0] dac_dds_phase_11_1 = 'd0;
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reg [ 15:0] dac_dds_phase_12_0 = 'd0;
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reg [ 15:0] dac_dds_phase_12_1 = 'd0;
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reg [ 15:0] dac_dds_phase_13_0 = 'd0;
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reg [ 15:0] dac_dds_phase_13_1 = 'd0;
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reg [ 15:0] dac_dds_phase_14_0 = 'd0;
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reg [ 15:0] dac_dds_phase_14_1 = 'd0;
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reg [ 15:0] dac_dds_phase_15_0 = 'd0;
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reg [ 15:0] dac_dds_phase_15_1 = 'd0;
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reg [ 15:0] dac_dds_incr_0 = 'd0;
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reg [ 15:0] dac_dds_incr_1 = 'd0;
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reg [ 15:0] dac_dds_data_00 = 'd0;
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reg [ 15:0] dac_dds_data_01 = 'd0;
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reg [ 15:0] dac_dds_data_02 = 'd0;
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reg [ 15:0] dac_dds_data_03 = 'd0;
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reg [ 15:0] dac_dds_data_04 = 'd0;
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reg [ 15:0] dac_dds_data_05 = 'd0;
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reg [ 15:0] dac_dds_data_06 = 'd0;
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reg [ 15:0] dac_dds_data_07 = 'd0;
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reg [ 15:0] dac_dds_data_08 = 'd0;
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reg [ 15:0] dac_dds_data_09 = 'd0;
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reg [ 15:0] dac_dds_data_10 = 'd0;
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reg [ 15:0] dac_dds_data_11 = 'd0;
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reg [ 15:0] dac_dds_data_12 = 'd0;
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reg [ 15:0] dac_dds_data_13 = 'd0;
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reg [ 15:0] dac_dds_data_14 = 'd0;
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reg [ 15:0] dac_dds_data_15 = 'd0;
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// internal signals
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wire [ 15:0] dac_dds_data_00_s;
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wire [ 15:0] dac_dds_data_01_s;
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wire [ 15:0] dac_dds_data_02_s;
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wire [ 15:0] dac_dds_data_03_s;
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wire [ 15:0] dac_dds_data_04_s;
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wire [ 15:0] dac_dds_data_05_s;
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wire [ 15:0] dac_dds_data_06_s;
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wire [ 15:0] dac_dds_data_07_s;
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wire [ 15:0] dac_dds_data_08_s;
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wire [ 15:0] dac_dds_data_09_s;
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wire [ 15:0] dac_dds_data_10_s;
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wire [ 15:0] dac_dds_data_11_s;
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wire [ 15:0] dac_dds_data_12_s;
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wire [ 15:0] dac_dds_data_13_s;
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wire [ 15:0] dac_dds_data_14_s;
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wire [ 15:0] dac_dds_data_15_s;
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wire [ 15:0] dac_dds_scale_1_s;
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wire [ 15:0] dac_dds_init_1_s;
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wire [ 15:0] dac_dds_incr_1_s;
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wire [ 15:0] dac_dds_scale_2_s;
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wire [ 15:0] dac_dds_init_2_s;
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wire [ 15:0] dac_dds_incr_2_s;
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wire [ 15:0] dac_pat_data_1_s;
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wire [ 15:0] dac_pat_data_2_s;
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wire [ 3:0] dac_data_sel_s;
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// dac data select
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always @(posedge dac_div_clk) begin
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dac_enable <= (dac_data_sel_s == 4'h2) ? 1'b1 : 1'b0;
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case (dac_data_sel_s)
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4'h2: begin
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dac_data_00 <= dma_data[ 15: 0];
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dac_data_01 <= dma_data[ 31: 16];
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dac_data_02 <= dma_data[ 47: 32];
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dac_data_03 <= dma_data[ 63: 48];
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dac_data_04 <= dma_data[ 79: 64];
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dac_data_05 <= dma_data[ 95: 80];
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dac_data_06 <= dma_data[111: 96];
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dac_data_07 <= dma_data[127:112];
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dac_data_08 <= dma_data[143:128];
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dac_data_09 <= dma_data[159:144];
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dac_data_10 <= dma_data[175:160];
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dac_data_11 <= dma_data[191:176];
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dac_data_12 <= dma_data[207:192];
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dac_data_13 <= dma_data[223:208];
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dac_data_14 <= dma_data[239:224];
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dac_data_15 <= dma_data[255:240];
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end
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4'h1: begin
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dac_data_00 <= dac_pat_data_1_s;
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dac_data_01 <= dac_pat_data_2_s;
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dac_data_02 <= dac_pat_data_1_s;
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dac_data_03 <= dac_pat_data_2_s;
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dac_data_04 <= dac_pat_data_1_s;
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dac_data_05 <= dac_pat_data_2_s;
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dac_data_06 <= dac_pat_data_1_s;
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dac_data_07 <= dac_pat_data_2_s;
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dac_data_08 <= dac_pat_data_1_s;
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dac_data_09 <= dac_pat_data_2_s;
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dac_data_10 <= dac_pat_data_1_s;
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dac_data_11 <= dac_pat_data_2_s;
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dac_data_12 <= dac_pat_data_1_s;
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dac_data_13 <= dac_pat_data_2_s;
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dac_data_14 <= dac_pat_data_1_s;
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dac_data_15 <= dac_pat_data_2_s;
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end
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default: begin
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dac_data_00 <= dac_dds_data_00;
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dac_data_01 <= dac_dds_data_01;
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dac_data_02 <= dac_dds_data_02;
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dac_data_03 <= dac_dds_data_03;
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dac_data_04 <= dac_dds_data_04;
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dac_data_05 <= dac_dds_data_05;
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dac_data_06 <= dac_dds_data_06;
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dac_data_07 <= dac_dds_data_07;
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dac_data_08 <= dac_dds_data_08;
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dac_data_09 <= dac_dds_data_09;
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dac_data_10 <= dac_dds_data_10;
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dac_data_11 <= dac_dds_data_11;
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dac_data_12 <= dac_dds_data_12;
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dac_data_13 <= dac_dds_data_13;
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dac_data_14 <= dac_dds_data_14;
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dac_data_15 <= dac_dds_data_15;
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end
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endcase
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end
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// single channel dds
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always @(posedge dac_div_clk) begin
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if (dac_data_sync == 1'b1) begin
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dac_dds_phase_00_0 <= dac_dds_init_1_s;
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dac_dds_phase_00_1 <= dac_dds_init_2_s;
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dac_dds_phase_01_0 <= dac_dds_phase_00_0 + dac_dds_incr_1_s;
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dac_dds_phase_01_1 <= dac_dds_phase_00_1 + dac_dds_incr_2_s;
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dac_dds_phase_02_0 <= dac_dds_phase_01_0 + dac_dds_incr_1_s;
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dac_dds_phase_02_1 <= dac_dds_phase_01_1 + dac_dds_incr_2_s;
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dac_dds_phase_03_0 <= dac_dds_phase_02_0 + dac_dds_incr_1_s;
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dac_dds_phase_03_1 <= dac_dds_phase_02_1 + dac_dds_incr_2_s;
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dac_dds_phase_04_0 <= dac_dds_phase_03_0 + dac_dds_incr_1_s;
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dac_dds_phase_04_1 <= dac_dds_phase_03_1 + dac_dds_incr_2_s;
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dac_dds_phase_05_0 <= dac_dds_phase_04_0 + dac_dds_incr_1_s;
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dac_dds_phase_05_1 <= dac_dds_phase_04_1 + dac_dds_incr_2_s;
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dac_dds_phase_06_0 <= dac_dds_phase_05_0 + dac_dds_incr_1_s;
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dac_dds_phase_06_1 <= dac_dds_phase_05_1 + dac_dds_incr_2_s;
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dac_dds_phase_07_0 <= dac_dds_phase_06_0 + dac_dds_incr_1_s;
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dac_dds_phase_07_1 <= dac_dds_phase_06_1 + dac_dds_incr_2_s;
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dac_dds_phase_08_0 <= dac_dds_phase_07_0 + dac_dds_incr_1_s;
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dac_dds_phase_08_1 <= dac_dds_phase_07_1 + dac_dds_incr_2_s;
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dac_dds_phase_09_0 <= dac_dds_phase_08_0 + dac_dds_incr_1_s;
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dac_dds_phase_09_1 <= dac_dds_phase_08_1 + dac_dds_incr_2_s;
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dac_dds_phase_10_0 <= dac_dds_phase_09_0 + dac_dds_incr_1_s;
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dac_dds_phase_10_1 <= dac_dds_phase_09_1 + dac_dds_incr_2_s;
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dac_dds_phase_11_0 <= dac_dds_phase_10_0 + dac_dds_incr_1_s;
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dac_dds_phase_11_1 <= dac_dds_phase_10_1 + dac_dds_incr_2_s;
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dac_dds_phase_12_0 <= dac_dds_phase_11_0 + dac_dds_incr_1_s;
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dac_dds_phase_12_1 <= dac_dds_phase_11_1 + dac_dds_incr_2_s;
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dac_dds_phase_13_0 <= dac_dds_phase_12_0 + dac_dds_incr_1_s;
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dac_dds_phase_13_1 <= dac_dds_phase_12_1 + dac_dds_incr_2_s;
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dac_dds_phase_14_0 <= dac_dds_phase_13_0 + dac_dds_incr_1_s;
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dac_dds_phase_14_1 <= dac_dds_phase_13_1 + dac_dds_incr_2_s;
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dac_dds_phase_15_0 <= dac_dds_phase_14_0 + dac_dds_incr_1_s;
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dac_dds_phase_15_1 <= dac_dds_phase_14_1 + dac_dds_incr_2_s;
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dac_dds_incr_0 <= {dac_dds_incr_1_s[11:0], 4'd0};
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dac_dds_incr_1 <= {dac_dds_incr_2_s[11:0], 4'd0};
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dac_dds_data_00 <= 15'd0;
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dac_dds_data_01 <= 15'd0;
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dac_dds_data_02 <= 15'd0;
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dac_dds_data_03 <= 15'd0;
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dac_dds_data_04 <= 15'd0;
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dac_dds_data_05 <= 15'd0;
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dac_dds_data_06 <= 15'd0;
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dac_dds_data_07 <= 15'd0;
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dac_dds_data_08 <= 15'd0;
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dac_dds_data_09 <= 15'd0;
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dac_dds_data_10 <= 15'd0;
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dac_dds_data_11 <= 15'd0;
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dac_dds_data_12 <= 15'd0;
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dac_dds_data_13 <= 15'd0;
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dac_dds_data_14 <= 15'd0;
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dac_dds_data_15 <= 15'd0;
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end else begin
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dac_dds_phase_00_0 <= dac_dds_phase_00_0 + dac_dds_incr_0;
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dac_dds_phase_00_1 <= dac_dds_phase_00_1 + dac_dds_incr_1;
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dac_dds_phase_01_0 <= dac_dds_phase_01_0 + dac_dds_incr_0;
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dac_dds_phase_01_1 <= dac_dds_phase_01_1 + dac_dds_incr_1;
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dac_dds_phase_02_0 <= dac_dds_phase_02_0 + dac_dds_incr_0;
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dac_dds_phase_02_1 <= dac_dds_phase_02_1 + dac_dds_incr_1;
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dac_dds_phase_03_0 <= dac_dds_phase_03_0 + dac_dds_incr_0;
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dac_dds_phase_03_1 <= dac_dds_phase_03_1 + dac_dds_incr_1;
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dac_dds_phase_04_0 <= dac_dds_phase_04_0 + dac_dds_incr_0;
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dac_dds_phase_04_1 <= dac_dds_phase_04_1 + dac_dds_incr_1;
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dac_dds_phase_05_0 <= dac_dds_phase_05_0 + dac_dds_incr_0;
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dac_dds_phase_05_1 <= dac_dds_phase_05_1 + dac_dds_incr_1;
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dac_dds_phase_06_0 <= dac_dds_phase_06_0 + dac_dds_incr_0;
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dac_dds_phase_06_1 <= dac_dds_phase_06_1 + dac_dds_incr_1;
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dac_dds_phase_07_0 <= dac_dds_phase_07_0 + dac_dds_incr_0;
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dac_dds_phase_07_1 <= dac_dds_phase_07_1 + dac_dds_incr_1;
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dac_dds_phase_08_0 <= dac_dds_phase_08_0 + dac_dds_incr_0;
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dac_dds_phase_08_1 <= dac_dds_phase_08_1 + dac_dds_incr_1;
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dac_dds_phase_09_0 <= dac_dds_phase_09_0 + dac_dds_incr_0;
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dac_dds_phase_09_1 <= dac_dds_phase_09_1 + dac_dds_incr_1;
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dac_dds_phase_10_0 <= dac_dds_phase_10_0 + dac_dds_incr_0;
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dac_dds_phase_10_1 <= dac_dds_phase_10_1 + dac_dds_incr_1;
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dac_dds_phase_11_0 <= dac_dds_phase_11_0 + dac_dds_incr_0;
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dac_dds_phase_11_1 <= dac_dds_phase_11_1 + dac_dds_incr_1;
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dac_dds_phase_12_0 <= dac_dds_phase_12_0 + dac_dds_incr_0;
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dac_dds_phase_12_1 <= dac_dds_phase_12_1 + dac_dds_incr_1;
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dac_dds_phase_13_0 <= dac_dds_phase_13_0 + dac_dds_incr_0;
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dac_dds_phase_13_1 <= dac_dds_phase_13_1 + dac_dds_incr_1;
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dac_dds_phase_14_0 <= dac_dds_phase_14_0 + dac_dds_incr_0;
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dac_dds_phase_14_1 <= dac_dds_phase_14_1 + dac_dds_incr_1;
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dac_dds_phase_15_0 <= dac_dds_phase_15_0 + dac_dds_incr_0;
|
|
dac_dds_phase_15_1 <= dac_dds_phase_15_1 + dac_dds_incr_1;
|
|
dac_dds_incr_0 <= dac_dds_incr_0;
|
|
dac_dds_incr_1 <= dac_dds_incr_1;
|
|
dac_dds_data_00 <= dac_dds_data_00_s;
|
|
dac_dds_data_01 <= dac_dds_data_01_s;
|
|
dac_dds_data_02 <= dac_dds_data_02_s;
|
|
dac_dds_data_03 <= dac_dds_data_03_s;
|
|
dac_dds_data_04 <= dac_dds_data_04_s;
|
|
dac_dds_data_05 <= dac_dds_data_05_s;
|
|
dac_dds_data_06 <= dac_dds_data_06_s;
|
|
dac_dds_data_07 <= dac_dds_data_07_s;
|
|
dac_dds_data_08 <= dac_dds_data_08_s;
|
|
dac_dds_data_09 <= dac_dds_data_09_s;
|
|
dac_dds_data_10 <= dac_dds_data_10_s;
|
|
dac_dds_data_11 <= dac_dds_data_11_s;
|
|
dac_dds_data_12 <= dac_dds_data_12_s;
|
|
dac_dds_data_13 <= dac_dds_data_13_s;
|
|
dac_dds_data_14 <= dac_dds_data_14_s;
|
|
dac_dds_data_15 <= dac_dds_data_15_s;
|
|
end
|
|
end
|
|
|
|
generate
|
|
if (DATAPATH_DISABLE == 1) begin
|
|
assign dac_dds_data_00_s = 16'd0;
|
|
end else begin
|
|
ad_dds i_dds_0 (
|
|
.clk (dac_div_clk),
|
|
.dds_format (dac_dds_format),
|
|
.dds_phase_0 (dac_dds_phase_00_0),
|
|
.dds_scale_0 (dac_dds_scale_1_s),
|
|
.dds_phase_1 (dac_dds_phase_00_1),
|
|
.dds_scale_1 (dac_dds_scale_2_s),
|
|
.dds_data (dac_dds_data_00_s));
|
|
end
|
|
endgenerate
|
|
|
|
generate
|
|
if (DATAPATH_DISABLE == 1) begin
|
|
assign dac_dds_data_01_s = 16'd0;
|
|
end else begin
|
|
ad_dds i_dds_1 (
|
|
.clk (dac_div_clk),
|
|
.dds_format (dac_dds_format),
|
|
.dds_phase_0 (dac_dds_phase_01_0),
|
|
.dds_scale_0 (dac_dds_scale_1_s),
|
|
.dds_phase_1 (dac_dds_phase_01_1),
|
|
.dds_scale_1 (dac_dds_scale_2_s),
|
|
.dds_data (dac_dds_data_01_s));
|
|
end
|
|
endgenerate
|
|
|
|
generate
|
|
if (DATAPATH_DISABLE == 1) begin
|
|
assign dac_dds_data_02_s = 16'd0;
|
|
end else begin
|
|
ad_dds i_dds_2 (
|
|
.clk (dac_div_clk),
|
|
.dds_format (dac_dds_format),
|
|
.dds_phase_0 (dac_dds_phase_02_0),
|
|
.dds_scale_0 (dac_dds_scale_1_s),
|
|
.dds_phase_1 (dac_dds_phase_02_1),
|
|
.dds_scale_1 (dac_dds_scale_2_s),
|
|
.dds_data (dac_dds_data_02_s));
|
|
end
|
|
endgenerate
|
|
|
|
generate
|
|
if (DATAPATH_DISABLE == 1) begin
|
|
assign dac_dds_data_03_s = 16'd0;
|
|
end else begin
|
|
ad_dds i_dds_3 (
|
|
.clk (dac_div_clk),
|
|
.dds_format (dac_dds_format),
|
|
.dds_phase_0 (dac_dds_phase_03_0),
|
|
.dds_scale_0 (dac_dds_scale_1_s),
|
|
.dds_phase_1 (dac_dds_phase_03_1),
|
|
.dds_scale_1 (dac_dds_scale_2_s),
|
|
.dds_data (dac_dds_data_03_s));
|
|
end
|
|
endgenerate
|
|
|
|
generate
|
|
if (DATAPATH_DISABLE == 1) begin
|
|
assign dac_dds_data_04_s = 16'd0;
|
|
end else begin
|
|
ad_dds i_dds_0 (
|
|
.clk (dac_div_clk),
|
|
.dds_format (dac_dds_format),
|
|
.dds_phase_0 (dac_dds_phase_04_0),
|
|
.dds_scale_0 (dac_dds_scale_1_s),
|
|
.dds_phase_1 (dac_dds_phase_04_1),
|
|
.dds_scale_1 (dac_dds_scale_2_s),
|
|
.dds_data (dac_dds_data_04_s));
|
|
end
|
|
endgenerate
|
|
|
|
generate
|
|
if (DATAPATH_DISABLE == 1) begin
|
|
assign dac_dds_data_05_s = 16'd0;
|
|
end else begin
|
|
ad_dds i_dds_0 (
|
|
.clk (dac_div_clk),
|
|
.dds_format (dac_dds_format),
|
|
.dds_phase_0 (dac_dds_phase_05_0),
|
|
.dds_scale_0 (dac_dds_scale_1_s),
|
|
.dds_phase_1 (dac_dds_phase_05_1),
|
|
.dds_scale_1 (dac_dds_scale_2_s),
|
|
.dds_data (dac_dds_data_05_s));
|
|
end
|
|
endgenerate
|
|
|
|
generate
|
|
if (DATAPATH_DISABLE == 1) begin
|
|
assign dac_dds_data_06_s = 16'd0;
|
|
end else begin
|
|
ad_dds i_dds_0 (
|
|
.clk (dac_div_clk),
|
|
.dds_format (dac_dds_format),
|
|
.dds_phase_0 (dac_dds_phase_06_0),
|
|
.dds_scale_0 (dac_dds_scale_1_s),
|
|
.dds_phase_1 (dac_dds_phase_06_1),
|
|
.dds_scale_1 (dac_dds_scale_2_s),
|
|
.dds_data (dac_dds_data_06_s));
|
|
end
|
|
endgenerate
|
|
|
|
generate
|
|
if (DATAPATH_DISABLE == 1) begin
|
|
assign dac_dds_data_07_s = 16'd0;
|
|
end else begin
|
|
ad_dds i_dds_0 (
|
|
.clk (dac_div_clk),
|
|
.dds_format (dac_dds_format),
|
|
.dds_phase_0 (dac_dds_phase_07_0),
|
|
.dds_scale_0 (dac_dds_scale_1_s),
|
|
.dds_phase_1 (dac_dds_phase_07_1),
|
|
.dds_scale_1 (dac_dds_scale_2_s),
|
|
.dds_data (dac_dds_data_07_s));
|
|
end
|
|
endgenerate
|
|
|
|
generate
|
|
if (DATAPATH_DISABLE == 1) begin
|
|
assign dac_dds_data_08_s = 16'd0;
|
|
end else begin
|
|
ad_dds i_dds_0 (
|
|
.clk (dac_div_clk),
|
|
.dds_format (dac_dds_format),
|
|
.dds_phase_0 (dac_dds_phase_08_0),
|
|
.dds_scale_0 (dac_dds_scale_1_s),
|
|
.dds_phase_1 (dac_dds_phase_08_1),
|
|
.dds_scale_1 (dac_dds_scale_2_s),
|
|
.dds_data (dac_dds_data_08_s));
|
|
end
|
|
endgenerate
|
|
|
|
generate
|
|
if (DATAPATH_DISABLE == 1) begin
|
|
assign dac_dds_data_09_s = 16'd0;
|
|
end else begin
|
|
ad_dds i_dds_0 (
|
|
.clk (dac_div_clk),
|
|
.dds_format (dac_dds_format),
|
|
.dds_phase_0 (dac_dds_phase_09_0),
|
|
.dds_scale_0 (dac_dds_scale_1_s),
|
|
.dds_phase_1 (dac_dds_phase_09_1),
|
|
.dds_scale_1 (dac_dds_scale_2_s),
|
|
.dds_data (dac_dds_data_09_s));
|
|
end
|
|
endgenerate
|
|
|
|
generate
|
|
if (DATAPATH_DISABLE == 1) begin
|
|
assign dac_dds_data_10_s = 16'd0;
|
|
end else begin
|
|
ad_dds i_dds_0 (
|
|
.clk (dac_div_clk),
|
|
.dds_format (dac_dds_format),
|
|
.dds_phase_0 (dac_dds_phase_10_0),
|
|
.dds_scale_0 (dac_dds_scale_1_s),
|
|
.dds_phase_1 (dac_dds_phase_10_1),
|
|
.dds_scale_1 (dac_dds_scale_2_s),
|
|
.dds_data (dac_dds_data_10_s));
|
|
end
|
|
endgenerate
|
|
|
|
generate
|
|
if (DATAPATH_DISABLE == 1) begin
|
|
assign dac_dds_data_11_s = 16'd0;
|
|
end else begin
|
|
ad_dds i_dds_0 (
|
|
.clk (dac_div_clk),
|
|
.dds_format (dac_dds_format),
|
|
.dds_phase_0 (dac_dds_phase_11_0),
|
|
.dds_scale_0 (dac_dds_scale_1_s),
|
|
.dds_phase_1 (dac_dds_phase_11_1),
|
|
.dds_scale_1 (dac_dds_scale_2_s),
|
|
.dds_data (dac_dds_data_11_s));
|
|
end
|
|
endgenerate
|
|
|
|
generate
|
|
if (DATAPATH_DISABLE == 1) begin
|
|
assign dac_dds_data_12_s = 16'd0;
|
|
end else begin
|
|
ad_dds i_dds_0 (
|
|
.clk (dac_div_clk),
|
|
.dds_format (dac_dds_format),
|
|
.dds_phase_0 (dac_dds_phase_12_0),
|
|
.dds_scale_0 (dac_dds_scale_1_s),
|
|
.dds_phase_1 (dac_dds_phase_12_1),
|
|
.dds_scale_1 (dac_dds_scale_2_s),
|
|
.dds_data (dac_dds_data_12_s));
|
|
end
|
|
endgenerate
|
|
|
|
generate
|
|
if (DATAPATH_DISABLE == 1) begin
|
|
assign dac_dds_data_13_s = 16'd0;
|
|
end else begin
|
|
ad_dds i_dds_0 (
|
|
.clk (dac_div_clk),
|
|
.dds_format (dac_dds_format),
|
|
.dds_phase_0 (dac_dds_phase_13_0),
|
|
.dds_scale_0 (dac_dds_scale_1_s),
|
|
.dds_phase_1 (dac_dds_phase_13_1),
|
|
.dds_scale_1 (dac_dds_scale_2_s),
|
|
.dds_data (dac_dds_data_13_s));
|
|
end
|
|
endgenerate
|
|
|
|
generate
|
|
if (DATAPATH_DISABLE == 1) begin
|
|
assign dac_dds_data_14_s = 16'd0;
|
|
end else begin
|
|
ad_dds i_dds_0 (
|
|
.clk (dac_div_clk),
|
|
.dds_format (dac_dds_format),
|
|
.dds_phase_0 (dac_dds_phase_14_0),
|
|
.dds_scale_0 (dac_dds_scale_1_s),
|
|
.dds_phase_1 (dac_dds_phase_14_1),
|
|
.dds_scale_1 (dac_dds_scale_2_s),
|
|
.dds_data (dac_dds_data_14_s));
|
|
end
|
|
endgenerate
|
|
|
|
generate
|
|
if (DATAPATH_DISABLE == 1) begin
|
|
assign dac_dds_data_15_s = 16'd0;
|
|
end else begin
|
|
ad_dds i_dds_0 (
|
|
.clk (dac_div_clk),
|
|
.dds_format (dac_dds_format),
|
|
.dds_phase_0 (dac_dds_phase_15_0),
|
|
.dds_scale_0 (dac_dds_scale_1_s),
|
|
.dds_phase_1 (dac_dds_phase_15_1),
|
|
.dds_scale_1 (dac_dds_scale_2_s),
|
|
.dds_data (dac_dds_data_15_s));
|
|
end
|
|
endgenerate
|
|
|
|
// single channel processor
|
|
|
|
up_dac_channel #(.CHANNEL_ID(CHANNEL_ID)) i_up_dac_channel (
|
|
.dac_clk (dac_div_clk),
|
|
.dac_rst (dac_rst),
|
|
.dac_dds_scale_1 (dac_dds_scale_1_s),
|
|
.dac_dds_init_1 (dac_dds_init_1_s),
|
|
.dac_dds_incr_1 (dac_dds_incr_1_s),
|
|
.dac_dds_scale_2 (dac_dds_scale_2_s),
|
|
.dac_dds_init_2 (dac_dds_init_2_s),
|
|
.dac_dds_incr_2 (dac_dds_incr_2_s),
|
|
.dac_pat_data_1 (dac_pat_data_1_s),
|
|
.dac_pat_data_2 (dac_pat_data_2_s),
|
|
.dac_data_sel (dac_data_sel_s),
|
|
.dac_iq_mode (),
|
|
.dac_iqcor_enb (),
|
|
.dac_iqcor_coeff_1 (),
|
|
.dac_iqcor_coeff_2 (),
|
|
.up_usr_datatype_be (),
|
|
.up_usr_datatype_signed (),
|
|
.up_usr_datatype_shift (),
|
|
.up_usr_datatype_total_bits (),
|
|
.up_usr_datatype_bits (),
|
|
.up_usr_interpolation_m (),
|
|
.up_usr_interpolation_n (),
|
|
.dac_usr_datatype_be (1'b0),
|
|
.dac_usr_datatype_signed (1'b1),
|
|
.dac_usr_datatype_shift (8'd0),
|
|
.dac_usr_datatype_total_bits (8'd16),
|
|
.dac_usr_datatype_bits (8'd16),
|
|
.dac_usr_interpolation_m (16'd1),
|
|
.dac_usr_interpolation_n (16'd1),
|
|
.up_rstn (up_rstn),
|
|
.up_clk (up_clk),
|
|
.up_wreq (up_wreq),
|
|
.up_waddr (up_waddr),
|
|
.up_wdata (up_wdata),
|
|
.up_wack (up_wack),
|
|
.up_rreq (up_rreq),
|
|
.up_raddr (up_raddr),
|
|
.up_rdata (up_rdata),
|
|
.up_rack (up_rack));
|
|
|
|
endmodule
|
|
|
|
// ***************************************************************************
|
|
// ***************************************************************************
|