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imoldovan 075ee05189
Update ad_data_in &_out (#1060) 
* ad_data_in: Add new logic and explanations

 * Added parameters IDELAY_TYPE, DELAY_FORMAT, US_DELAY_TYPE to be used
   with the IDELAY instances
 * Added explanations
 * Added option to bypass IDELAY if it's not instantiated, regardless of
   the FPGA_TECHNOLOGY parameter
 * Determined a part of the logic for EN_VTC (by the UG) but not for all
   modes since we don't have use cases for them
 * Changed logic when adding ODELAY: now you must set IODELAY_ENABLE = 1
   and FPGA_TECHNOLOGY != NONE if you want it

* ad_data_out:

 * Updated ODDR parameter
 * Fixed issue with ODDR inputs D1, D2: D1 must be with _p and D2 with _n,
   according to the Xilinx template
 * Removed _ES1 from IODELAY_SIM_DEVICE

 * Added ODELAY for UltraScale
 * Before, there was no support for UltraScale/+, and the output data
   was completely disconnected from the ODDR
 * The support for this was requested in this issue, although as of now we don't
   have a design that uses it: https://github.com/analogdevicesinc/hdl/issues/917

 * Added parameters ODELAY_TYPE, DELAY_FORMAT, US_DELAY_TYPE to be used
   with the ODELAY instances
 * Added explanations
 * Added option to bypass ODELAY if it's not instantiated, regardless of
   the FPGA_TECHNOLOGY parameter
 * Determined a part of the logic for the EN_VTC (by the UG) but not for
   all modes since we don't have use cases for them
 * Changed logic when adding ODELAY: now you must set IODELAY_ENABLE = 1
   and FPGA_TECHNOLOGY != NONE if you want it

---------

Signed-off-by: Iulia Moldovan <Iulia.Moldovan@analog.com>
 		2023-04-04 11:09:46 +03:00
.github check_guideline.py: Add execute permissions 2023-03-15 17:47:46 +02:00
docs docs/regmap: Updates on regmap text files to match the Wiki page updates. 2023-03-14 10:08:03 +02:00
library Update ad_data_in &_out (#1060) 2023-04-04 11:09:46 +03:00
projects cn0561_de10nano: Initial commit 2023-03-30 14:55:59 +03:00
scripts adi_env.tcl: Update Vivado version to 2022.2 2023-03-09 09:53:41 +02:00
.gitattributes Update .gitattributes 2016-02-12 14:27:35 +02:00
.gitignore .gitignore: ignore files generated by Quartus & Platform Designer 2022-06-09 11:32:10 +03:00
LICENSE Make system: Be explicit in license that cover the make/build system 2021-09-16 16:50:53 +03:00
LICENSE_ADIBSD Make system: Be explicit in license that cover the make/build system 2021-09-16 16:50:53 +03:00
LICENSE_BSD-1-Clause Make system: Be explicit in license that cover the make/build system 2021-09-16 16:50:53 +03:00
LICENSE_GPL2 license: Add top level license files 2017-05-29 09:57:39 +03:00
LICENSE_LGPL License: Update LGPL to version 2.1 2020-03-06 16:07:18 +02:00
Makefile Makefiles: Update header with the appropriate license 2021-09-16 16:50:53 +03:00
README.md README.md: Add link to boot partition files download link 2021-12-07 14:42:42 +02:00
quiet.mk Make system: Be explicit in license that cover the make/build system 2021-09-16 16:50:53 +03:00

README.md

HDL Reference Designs

Analog Devices Inc. HDL libraries and projects for various reference design and prototyping systems. This repository contains HDL code (Verilog or VHDL) and the required Tcl scripts to create and build a specific FPGA example design using Xilinx and/or Intel tool chain.

Support

The HDL is provided "AS IS", support is only provided on EngineerZone.

If you feel you can not, or do not want to ask questions on EngineerZone, you should not use or look at the HDL found in this repository. Just like you have the freedom and rights to use this software in your products (with the obligations found in individual licenses) and get support on EngineerZone, you have the freedom and rights not to use this software and get datasheet level support from traditional ADI contacts that you may have.

There is no free replacement for consulting services. If you have questions that are best handed one-on-one engagement, and are time sensitive, consider hiring a consultant. If you want to find a consultant who is familar with the HDL found in this repository - ask on EngineerZone.

Getting started

This repository supports reference designs for different Analog Devices boards based on Intel and Xilinx FPGA development boards or standalone.

Prerequisites

or

Please make sure that you have the required tool version.

How to build a project

For building a project (generate a bitstream), you have to use the GNU Make tool. If you're a Windows user please checkout this page, to see how you can install this tool.

To build a project, checkout the latest release, after that just cd to the project that you want to build and run make:

 [~]cd projects/fmcomms2/zc706
 [~]make

A more comprehensive build guide can be found under the following link: https://wiki.analog.com/resources/fpga/docs/build

Software

In general all the projects have no-OS (baremetal) and a Linux support. See no-OS or Linux for more information.

Which branch should I use?

Use already built files

You can download already built files and use them as they are. They are available on this link.
The files are built from master branch whenever there are new commits in HDL or Linux repositories.

⚠️ Pay attention when using already built files, since they are not tested in HW!

License

In this HDL repository, there are many different and unique modules, consisting of various HDL (Verilog or VHDL) components. The individual modules are developed independently, and may be accompanied by separate and unique license terms.

The user should read each of these license terms, and understand the freedoms and responsibilities that he or she has by using this source/core.

See LICENSE for more details. The separate license files cab be found here:

Comprehensive user guide

See HDL User Guide for a more detailed guide.