215 lines
5.7 KiB
Verilog
215 lines
5.7 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
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//
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// Each core or library found in this collection may have its own licensing terms.
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// The user should keep this in in mind while exploring these cores.
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//
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// Redistribution and use in source and binary forms,
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// with or without modification of this file, are permitted under the terms of either
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// (at the option of the user):
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//
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// 1. The GNU General Public License version 2 as published by the
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// Free Software Foundation, which can be found in the top level directory, or at:
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// https://www.gnu.org/licenses/old-licenses/gpl-2.0.en.html
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//
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// OR
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//
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// 2. An ADI specific BSD license as noted in the top level directory, or on-line at:
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// https://github.com/analogdevicesinc/hdl/blob/dev/LICENSE
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//
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module axi_ad9963_tx #(
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// parameters
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parameter DATAPATH_DISABLE = 0,
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parameter ID = 0) (
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// dac interface
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input dac_clk,
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output dac_rst,
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output reg dac_valid,
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output [23:0] dac_data,
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input [23:0] adc_data,
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// master/slave
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input dac_sync_in,
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output dac_sync_out,
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// dma interface
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output dac_enable_i,
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output reg dac_valid_i,
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input [15:0] dac_data_i,
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output dac_enable_q,
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output reg dac_valid_q,
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input [15:0] dac_data_q,
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input dac_dovf,
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input dac_dunf,
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output up_dac_ce,
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// processor interface
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input up_rstn,
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input up_clk,
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input up_wreq,
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input [13:0] up_waddr,
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input [31:0] up_wdata,
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output reg up_wack,
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input up_rreq,
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input [13:0] up_raddr,
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output reg [31:0] up_rdata,
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output reg up_rack);
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// internal signals
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wire dac_data_sync_s;
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wire dac_dds_format_s;
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wire [23:0] dac_data_int_s;
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wire [31:0] up_rdata_s[0:2];
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wire up_rack_s[0:2];
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wire up_wack_s[0:2];
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// master/slave
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assign dac_data_sync_s = (ID == 0) ? dac_sync_out : dac_sync_in;
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// dma interface
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always @(posedge dac_clk) begin
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if (dac_rst == 1'b1) begin
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dac_valid <= 1'b0;
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dac_valid_i <= 1'b0;
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dac_valid_q <= 1'b0;
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end else begin
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dac_valid <= 1'b1;
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dac_valid_i <= dac_valid;
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dac_valid_q <= dac_valid;
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end
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end
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// processor read interface
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always @(*) begin
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up_rdata <= up_rdata_s[0] | up_rdata_s[1] | up_rdata_s[2];
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up_rack <= up_rack_s[0] | up_rack_s[1] | up_rack_s[2];
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up_wack <= up_wack_s[0] | up_wack_s[1] | up_wack_s[2];
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end
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// dac channel
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axi_ad9963_tx_channel #(
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.CHANNEL_ID (0),
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.Q_OR_I_N (0),
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.DATAPATH_DISABLE (DATAPATH_DISABLE))
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i_tx_channel_0 (
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.dac_clk (dac_clk),
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.dac_rst (dac_rst),
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.dac_valid (dac_valid),
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.dma_data (dac_data_i),
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.adc_data (adc_data[11:0]),
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.dac_data (dac_data[11:0]),
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.dac_data_out (dac_data_int_s[11:0]),
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.dac_data_in (dac_data_int_s[23:12]),
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.dac_enable (dac_enable_i),
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.dac_data_sync (dac_data_sync_s),
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.dac_dds_format (dac_dds_format_s),
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.up_rstn (up_rstn),
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.up_clk (up_clk),
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.up_wreq (up_wreq),
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.up_waddr (up_waddr),
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.up_wdata (up_wdata),
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.up_wack (up_wack_s[0]),
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.up_rreq (up_rreq),
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.up_raddr (up_raddr),
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.up_rdata (up_rdata_s[0]),
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.up_rack (up_rack_s[0]));
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// dac channel
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axi_ad9963_tx_channel #(
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.CHANNEL_ID (1),
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.Q_OR_I_N (1),
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.DATAPATH_DISABLE (DATAPATH_DISABLE))
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i_tx_channel_1 (
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.dac_clk (dac_clk),
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.dac_rst (dac_rst),
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.dac_valid (dac_valid),
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.dma_data (dac_data_q),
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.adc_data (adc_data[23:12]),
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.dac_data (dac_data[23:12]),
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.dac_data_out (dac_data_int_s[23:12]),
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.dac_data_in (dac_data_int_s[11:0]),
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.dac_enable (dac_enable_q),
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.dac_data_sync (dac_data_sync_s),
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.dac_dds_format (dac_dds_format_s),
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.up_rstn (up_rstn),
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.up_clk (up_clk),
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.up_wreq (up_wreq),
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.up_waddr (up_waddr),
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.up_wdata (up_wdata),
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.up_wack (up_wack_s[1]),
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.up_rreq (up_rreq),
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.up_raddr (up_raddr),
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.up_rdata (up_rdata_s[1]),
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.up_rack (up_rack_s[1]));
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// dac common processor interface
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up_dac_common #(
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.ID (ID),
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.DRP_DISABLE (1),
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.USERPORTS_DISABLE (1),
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.GPIO_DISABLE(1)
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) i_up_dac_common (
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.mmcm_rst (),
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.dac_clk (dac_clk),
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.dac_rst (dac_rst),
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.dac_sync (dac_sync_out),
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.dac_frame (),
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.dac_clksel(),
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.dac_par_type (),
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.dac_par_enb (),
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.dac_r1_mode (),
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.dac_datafmt (dac_dds_format_s),
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.dac_datarate (),
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.dac_status (1'b1),
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.dac_status_ovf (dac_dovf),
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.dac_status_unf (dac_dunf),
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.dac_clk_ratio (32'd1),
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.up_dac_ce(up_dac_ce),
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.up_drp_sel (),
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.up_drp_wr (),
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.up_drp_addr (),
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.up_drp_wdata (),
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.up_drp_rdata (16'd0),
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.up_drp_ready (1'd0),
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.up_drp_locked (1'd1),
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.up_usr_chanmax (),
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.dac_usr_chanmax (8'd2),
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.up_dac_gpio_in (32'h0),
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.up_dac_gpio_out (),
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.up_rstn (up_rstn),
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.up_clk (up_clk),
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.up_wreq (up_wreq),
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.up_waddr (up_waddr),
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.up_wdata (up_wdata),
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.up_wack (up_wack_s[2]),
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.up_rreq (up_rreq),
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.up_raddr (up_raddr),
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.up_rdata (up_rdata_s[2]),
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.up_rack (up_rack_s[2]));
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endmodule
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// ***************************************************************************
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// ***************************************************************************
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