213 lines
6.3 KiB
Verilog
213 lines
6.3 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
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//
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// Each core or library found in this collection may have its own licensing terms.
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// The user should keep this in in mind while exploring these cores.
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//
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// Redistribution and use in source and binary forms,
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// with or without modification of this file, are permitted under the terms of either
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// (at the option of the user):
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//
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// 1. The GNU General Public License version 2 as published by the
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// Free Software Foundation, which can be found in the top level directory, or at:
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// https://www.gnu.org/licenses/old-licenses/gpl-2.0.en.html
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//
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// OR
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//
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// 2. An ADI specific BSD license as noted in the top level directory, or on-line at:
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// https://github.com/analogdevicesinc/hdl/blob/dev/LICENSE
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//
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module up_axi #(
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parameter ADDRESS_WIDTH = 14,
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parameter AXI_ADDRESS_WIDTH = 32) (
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// reset and clocks
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input up_rstn,
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input up_clk,
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// axi4 interface
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input up_axi_awvalid,
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input [AXI_AW:0] up_axi_awaddr,
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output reg up_axi_awready,
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input up_axi_wvalid,
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input [31:0] up_axi_wdata,
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input [ 3:0] up_axi_wstrb,
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output reg up_axi_wready,
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output reg up_axi_bvalid,
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output [ 1:0] up_axi_bresp,
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input up_axi_bready,
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input up_axi_arvalid,
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input [AXI_AW:0] up_axi_araddr,
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output reg up_axi_arready,
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output reg up_axi_rvalid,
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output [ 1:0] up_axi_rresp,
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output reg [31:0] up_axi_rdata,
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input up_axi_rready,
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// pcore interface
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output reg up_wreq,
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output reg [AW:0] up_waddr,
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output reg [31:0] up_wdata,
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input up_wack,
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output reg up_rreq,
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output reg [AW:0] up_raddr,
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input [31:0] up_rdata,
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input up_rack);
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localparam AXI_AW = AXI_ADDRESS_WIDTH - 1;
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localparam AW = ADDRESS_WIDTH - 1;
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// internal registers
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reg up_wack_d = 'd0;
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reg up_wsel = 'd0;
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reg [ 4:0] up_wcount = 'd0;
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reg up_rack_d = 'd0;
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reg [31:0] up_rdata_d = 'd0;
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reg up_rsel = 'd0;
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reg [ 4:0] up_rcount = 'd0;
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// internal signals
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wire up_wack_s;
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wire up_rack_s;
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wire [31:0] up_rdata_s;
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// write channel interface
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assign up_axi_bresp = 2'd0;
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always @(negedge up_rstn or posedge up_clk) begin
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if (up_rstn == 1'b0) begin
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up_axi_awready <= 'd0;
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up_axi_wready <= 'd0;
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up_axi_bvalid <= 'd0;
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end else begin
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if (up_axi_awready == 1'b1) begin
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up_axi_awready <= 1'b0;
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end else if (up_wack_s == 1'b1) begin
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up_axi_awready <= 1'b1;
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end
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if (up_axi_wready == 1'b1) begin
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up_axi_wready <= 1'b0;
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end else if (up_wack_s == 1'b1) begin
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up_axi_wready <= 1'b1;
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end
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if ((up_axi_bready == 1'b1) && (up_axi_bvalid == 1'b1)) begin
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up_axi_bvalid <= 1'b0;
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end else if (up_wack_d == 1'b1) begin
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up_axi_bvalid <= 1'b1;
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end
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end
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end
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assign up_wack_s = (up_wcount == 5'h1f) ? 1'b1 : (up_wcount[4] & up_wack);
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always @(negedge up_rstn or posedge up_clk) begin
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if (up_rstn == 1'b0) begin
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up_wack_d <= 'd0;
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up_wsel <= 'd0;
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up_wreq <= 'd0;
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up_waddr <= 'd0;
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up_wdata <= 'd0;
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up_wcount <= 'd0;
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end else begin
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up_wack_d <= up_wack_s;
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if (up_wsel == 1'b1) begin
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if ((up_axi_bready == 1'b1) && (up_axi_bvalid == 1'b1)) begin
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up_wsel <= 1'b0;
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end
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up_wreq <= 1'b0;
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up_waddr <= up_waddr;
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up_wdata <= up_wdata;
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end else begin
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up_wsel <= up_axi_awvalid & up_axi_wvalid;
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up_wreq <= up_axi_awvalid & up_axi_wvalid;
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up_waddr <= up_axi_awaddr[AW+2:2];
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up_wdata <= up_axi_wdata;
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end
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if (up_wack_s == 1'b1) begin
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up_wcount <= 5'h00;
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end else if (up_wcount[4] == 1'b1) begin
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up_wcount <= up_wcount + 1'b1;
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end else if (up_wreq == 1'b1) begin
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up_wcount <= 5'h10;
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end
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end
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end
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// read channel interface
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assign up_axi_rresp = 2'd0;
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always @(negedge up_rstn or posedge up_clk) begin
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if (up_rstn == 1'b0) begin
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up_axi_arready <= 'd0;
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up_axi_rvalid <= 'd0;
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up_axi_rdata <= 'd0;
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end else begin
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if (up_axi_arready == 1'b1) begin
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up_axi_arready <= 1'b0;
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end else if (up_rack_s == 1'b1) begin
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up_axi_arready <= 1'b1;
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end
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if ((up_axi_rready == 1'b1) && (up_axi_rvalid == 1'b1)) begin
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up_axi_rvalid <= 1'b0;
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up_axi_rdata <= 32'd0;
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end else if (up_rack_d == 1'b1) begin
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up_axi_rvalid <= 1'b1;
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up_axi_rdata <= up_rdata_d;
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end
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end
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end
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assign up_rack_s = (up_rcount == 5'h1f) ? 1'b1 : (up_rcount[4] & up_rack);
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assign up_rdata_s = (up_rcount == 5'h1f) ? {2{16'hdead}} : up_rdata;
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always @(negedge up_rstn or posedge up_clk) begin
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if (up_rstn == 1'b0) begin
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up_rack_d <= 'd0;
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up_rdata_d <= 'd0;
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up_rsel <= 'd0;
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up_rreq <= 'd0;
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up_raddr <= 'd0;
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up_rcount <= 'd0;
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end else begin
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up_rack_d <= up_rack_s;
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up_rdata_d <= up_rdata_s;
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if (up_rsel == 1'b1) begin
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if ((up_axi_rready == 1'b1) && (up_axi_rvalid == 1'b1)) begin
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up_rsel <= 1'b0;
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end
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up_rreq <= 1'b0;
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up_raddr <= up_raddr;
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end else begin
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up_rsel <= up_axi_arvalid;
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up_rreq <= up_axi_arvalid;
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up_raddr <= up_axi_araddr[AW+2:2];
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end
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if (up_rack_s == 1'b1) begin
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up_rcount <= 5'h00;
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end else if (up_rcount[4] == 1'b1) begin
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up_rcount <= up_rcount + 1'b1;
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end else if (up_rreq == 1'b1) begin
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up_rcount <= 5'h10;
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end
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end
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end
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endmodule
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// ***************************************************************************
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// ***************************************************************************
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