Laszlo Nagy 0261eade0c zynq:all: fix SPI clock constraint ... According to data sheets the EMIO SPI controller maximum frequency is just 25MHz. Constrain the SPI clock accordingly.		2019-08-09 16:39:56 +03:00
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zc706_plddr3_adcfifo_bd.tcl	zc706/plddr3_adc|dacfifo_bd: PL DDR3 size is 1Gbyte	2019-05-06 17:17:00 +03:00
zc706_plddr3_constr.xdc	plddr3- change to board files	2017-02-22 15:22:50 -05:00
zc706_plddr3_dacfifo_bd.tcl	zc706/plddr3_adc|dacfifo_bd: PL DDR3 size is 1Gbyte	2019-05-06 17:17:00 +03:00
zc706_plddr3_mig.prj	plddr3- change to board files	2017-02-22 15:22:50 -05:00
zc706_system_bd.tcl	system_id: deployed ip	2019-08-06 16:53:11 +03:00
zc706_system_constr.xdc	zynq:all: fix SPI clock constraint	2019-08-09 16:39:56 +03:00