105 lines
4.0 KiB
Verilog
105 lines
4.0 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2011-2013(c) Analog Devices, Inc.
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//
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without modification,
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// are permitted provided that the following conditions are met:
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// - Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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// - Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in
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// the documentation and/or other materials provided with the
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// distribution.
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// - Neither the name of Analog Devices, Inc. nor the names of its
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// contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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// - The use of this software may or may not infringe the patent rights
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// of one or more patent holders. This license does not release you
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// from the requirement that you obtain separate licenses from these
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// patent holders to use this software.
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// - Use of the software either in source or binary form, must be run
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// on or directly connected to an Analog Devices Inc. component.
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//
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// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
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// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
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// PARTICULAR PURPOSE ARE DISCLAIMED.
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//
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// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
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// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
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// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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module embedded_sync_decoder(
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input clk,
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input [15:0] data_in,
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output reg hs_de,
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output reg vs_de,
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output reg [15:0] data_out
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);
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reg [15:0] data_d = 'd0;
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reg hs_de_rcv_d = 'd0;
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reg vs_de_rcv_d = 'd0;
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reg [15:0] data_2d = 'd0;
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reg hs_de_rcv_2d = 'd0;
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reg vs_de_rcv_2d = 'd0;
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reg [15:0] data_3d = 'd0;
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reg hs_de_rcv_3d = 'd0;
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reg vs_de_rcv_3d = 'd0;
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reg [15:0] data_4d = 'd0;
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reg hs_de_rcv_4d = 'd0;
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reg vs_de_rcv_4d = 'd0;
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reg hs_de_rcv = 'd0;
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reg vs_de_rcv = 'd0;
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// delay to get rid of eav's 4 bytes
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always @(posedge clk) begin
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data_d <= data_in;
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data_2d <= data_d;
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data_3d <= data_2d;
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data_4d <= data_3d;
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data_out <= data_4d;
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hs_de_rcv_d <= hs_de_rcv;
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vs_de_rcv_d <= vs_de_rcv;
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hs_de_rcv_2d <= hs_de_rcv_d;
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vs_de_rcv_2d <= vs_de_rcv_d;
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hs_de_rcv_3d <= hs_de_rcv_2d;
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vs_de_rcv_3d <= vs_de_rcv_2d;
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hs_de_rcv_4d <= hs_de_rcv_3d;
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vs_de_rcv_4d <= vs_de_rcv_3d;
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hs_de <= hs_de_rcv & hs_de_rcv_4d;
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vs_de <= vs_de_rcv & vs_de_rcv_4d;
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end
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reg [1:0] preamble_cnt = 'd0;
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// check for sav and eav and generate the corresponding enables
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always @(posedge clk) begin
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if ((data_in == 16'hffff) || (data_in == 16'h0000)) begin
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preamble_cnt <= preamble_cnt + 1'b1;
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end else begin
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preamble_cnt <= 'd0;
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end
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if (preamble_cnt == 3'h3) begin
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if ((data_in == 16'hb6b6) || (data_in == 16'h9d9d)) begin
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hs_de_rcv <= 1'b0;
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vs_de_rcv <= ~data_in[13];
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end else if ((data_in == 16'habab) || (data_in == 16'h8080)) begin
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hs_de_rcv <= 1'b1;
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vs_de_rcv <= ~data_in[13];
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end
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end
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end
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endmodule
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