Iulia Moldovan fe713a5e98 library/axi_dmac: Rename 2d_transfer to dmac_2d_transfer ... Update the file according to HDL guideline. Replace all occurrences of 2d_transfer with dmac_2d_transfer. Update axi_dmac/Makefile.		2022-04-01 16:02:46 +03:00
..
axi_read_slave.v	axi_dmac: tb: Allow testing asymmetric interface widths	2018-11-30 23:41:49 +02:00
axi_slave.v	axi_dmac: tb: Allow testing asymmetric interface widths	2018-11-30 23:41:49 +02:00
axi_write_slave.v	axi_dmac: tb: Allow testing asymmetric interface widths	2018-11-30 23:41:49 +02:00
dma_read_shutdown_tb	library/axi_dmac: Rename 2d_transfer to dmac_2d_transfer	2022-04-01 16:02:46 +03:00
dma_read_shutdown_tb.v	Testbenches: Unify and optimize HDL testbenches	2021-05-07 19:53:14 +03:00
dma_read_tb	library/axi_dmac: Rename 2d_transfer to dmac_2d_transfer	2022-04-01 16:02:46 +03:00
dma_read_tb.v	Testbenches: Unify and optimize HDL testbenches	2021-05-07 19:53:14 +03:00
dma_write_shutdown_tb	library/axi_dmac: Rename 2d_transfer to dmac_2d_transfer	2022-04-01 16:02:46 +03:00
dma_write_shutdown_tb.v	Testbenches: Unify and optimize HDL testbenches	2021-05-07 19:53:14 +03:00
dma_write_tb	library/axi_dmac: Rename 2d_transfer to dmac_2d_transfer	2022-04-01 16:02:46 +03:00
dma_write_tb.v	Testbenches: Unify and optimize HDL testbenches	2021-05-07 19:53:14 +03:00
regmap_tb	Testbenches: Unify and optimize HDL testbenches	2021-05-07 19:53:14 +03:00
regmap_tb.v	axi_dmac: Restore axi_dmac_regmap_request to f7b8a2d version	2021-07-02 15:52:48 +03:00
reset_manager_tb	Testbenches: Unify and optimize HDL testbenches	2021-05-07 19:53:14 +03:00
reset_manager_tb.v	Testbenches: Unify and optimize HDL testbenches	2021-05-07 19:53:14 +03:00
tb_base.v	tb_base: Fix various test benches	2019-05-17 11:20:48 +03:00