102 lines
4.2 KiB
Plaintext
102 lines
4.2 KiB
Plaintext
#
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# The ADI JESD204 Core is released under the following license, which is
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# different than all other HDL cores in this repository.
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#
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# Please read this, and understand the freedoms and responsibilities you have
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# by using this source code/core.
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#
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# The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
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#
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# This core is free software, you can use run, copy, study, change, ask
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# questions about and improve this core. Distribution of source, or resulting
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# binaries (including those inside an FPGA or ASIC) require you to release the
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# source of the entire project (excluding the system libraries provide by the
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# tools/compiler/FPGA vendor). These are the terms of the GNU General Public
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# License version 2 as published by the Free Software Foundation.
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#
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# This core is distributed in the hope that it will be useful, but WITHOUT ANY
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# WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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# A PARTICULAR PURPOSE. See the GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License version 2
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# along with this source code, and binary. If not, see
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# <http://www.gnu.org/licenses/>.
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#
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# Commercial licenses (with commercial support) of this JESD204 core are also
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# available under terms different than the General Public License. (e.g. they
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# do not require you to accompany any image (FPGA or ASIC) using the JESD204
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# core with any corresponding source code.) For these alternate terms you must
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# purchase a license from Analog Devices Technology Licensing Office. Users
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# interested in such a license should contact jesd204-licensing@analog.com for
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# more information. This commercial license is sub-licensable (if you purchase
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# chips from Analog Devices, incorporate them into your PCB level product, and
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# purchase a JESD204 license, end users of your product will also have a
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# license to use this core in a commercial setting without releasing their
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# source code).
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#
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# In addition, we kindly ask you to acknowledge ADI in any program, application
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# or publication in which you use this JESD204 HDL core. (You are not required
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# to do so; it is up to your common sense to decide whether you want to comply
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# with this request or not.) For general publications, we suggest referencing :
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# “The design and implementation of the JESD204 HDL Core used in this project
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# is copyright © 2016-2017, Analog Devices, Inc.”
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#
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<: set ComponentName [getComponentNameString] :>
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<: setOutputDirectory "./" :>
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<: setFileName [ttcl_add $ComponentName "_constr"] :>
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<: setFileExtension ".xdc" :>
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<: setFileProcessingOrder late :>
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<: set sysref_iob [get_property PARAM_VALUE.SYSREF_IOB] :>
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<: set async_clk [getBooleanValue "ASYNC_CLK"] :>
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set_property ASYNC_REG TRUE \
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[get_cells {i_lmfc/sysref_d1_reg}] \
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[get_cells {i_lmfc/sysref_d2_reg}]
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# Make sure that the device clock to sysref skew is at least somewhat
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# predictable
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set_property IOB <=: $sysref_iob :> \
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[get_cells {i_lmfc/sysref_r_reg}]
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<: if {$async_clk} { :>
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set link_clk [get_clocks -of_objects [get_ports -quiet {clk}]]
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set device_clk [get_clocks -of_objects [get_ports -quiet {device_clk}]]
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# sync event i_sync_lmfc
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set_false_path -quiet \
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-from $device_clk \
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-to [get_cells -quiet -hier *cdc_sync_stage1_reg* \
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-filter {NAME =~ *i_sync_lmfc/i_sync_out* && IS_SEQUENTIAL}]
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set_false_path -quiet \
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-from $link_clk \
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-to [get_cells -quiet -hier *cdc_sync_stage1_reg* \
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-filter {NAME =~ *i_sync_lmfc/i_sync_in* && IS_SEQUENTIAL}]
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# sync bits i_next_mf_ready_cdc
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set_false_path \
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-from $link_clk \
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-to [get_cells -quiet -hier *cdc_sync_stage1_reg* \
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-filter {NAME =~ *i_next_mf_ready_cdc* && IS_SEQUENTIAL}]
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# sync bits i_link_reset_done_cdc
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set_false_path \
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-from $link_clk \
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-to [get_cells -quiet -hier *cdc_sync_stage1_reg* \
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-filter {NAME =~ *i_link_reset_done_cdc* && IS_SEQUENTIAL}]
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# sync bits gearbox/i_sync_ready
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set_false_path \
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-from $link_clk \
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-to [get_cells -quiet -hier *cdc_sync_stage1_reg* \
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-filter {NAME =~ *i_sync_ready* && IS_SEQUENTIAL}]
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# gearbox distributed RAM
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set_false_path -quiet \
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-from $device_clk \
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-to [get_cells -quiet -hier *mem_rd_data_reg* \
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-filter {NAME =~ *i_tx_gearbox* && IS_SEQUENTIAL}]
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<: } :>
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