393 lines
12 KiB
Verilog
393 lines
12 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2014 - 2020 (c) Analog Devices, Inc. All rights reserved.
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//
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// In this HDL repository, there are many different and unique modules, consisting
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// of various HDL (Verilog or VHDL) components. The individual modules are
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// developed independently, and may be accompanied by separate and unique license
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// terms.
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//
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// The user should read each of these license terms, and understand the
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// freedoms and responsibilities that he or she has by using this source/core.
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//
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// This core is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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// A PARTICULAR PURPOSE.
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//
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// Redistribution and use of source or resulting binaries, with or without modification
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// of this file, are permitted under one of the following two license terms:
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//
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// 1. The GNU General Public License version 2 as published by the
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// Free Software Foundation, which can be found in the top level directory
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// of this repository (LICENSE_GPL2), and also online at:
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// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
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//
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// OR
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//
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// 2. An ADI specific BSD license, which can be found in the top level directory
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// of this repository (LICENSE_ADIBSD), and also on-line at:
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// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
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// This will allow to generate bit files and not release the source code,
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// as long as it attaches to an ADI device.
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//
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module system_top (
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inout [14:0] ddr_addr,
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inout [ 2:0] ddr_ba,
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inout ddr_cas_n,
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inout ddr_ck_n,
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inout ddr_ck_p,
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inout ddr_cke,
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inout ddr_cs_n,
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inout [ 3:0] ddr_dm,
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inout [31:0] ddr_dq,
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inout [ 3:0] ddr_dqs_n,
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inout [ 3:0] ddr_dqs_p,
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inout ddr_odt,
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inout ddr_ras_n,
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inout ddr_reset_n,
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inout ddr_we_n,
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inout fixed_io_ddr_vrn,
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inout fixed_io_ddr_vrp,
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inout [53:0] fixed_io_mio,
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inout fixed_io_ps_clk,
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inout fixed_io_ps_porb,
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inout fixed_io_ps_srstb,
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inout [31:0] gpio_bd,
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output hdmi_out_clk,
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output hdmi_vsync,
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output hdmi_hsync,
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output hdmi_data_e,
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output [15:0] hdmi_data,
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output i2s_mclk,
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output i2s_bclk,
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output i2s_lrclk,
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output i2s_sdata_out,
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input i2s_sdata_in,
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output spdif,
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inout iic_scl,
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inout iic_sda,
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inout [ 1:0] iic_mux_scl,
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inout [ 1:0] iic_mux_sda,
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input otg_vbusoc,
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// FMC connector
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output spi_clk,
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output spi_dio,
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input spi_do,
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output spi_en,
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// Device clock passed through 9001
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input dev_clk_out,
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inout dgpio_0,
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inout dgpio_1,
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inout dgpio_2,
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inout dgpio_3,
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inout dgpio_4,
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inout dgpio_5,
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inout dgpio_6,
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inout dgpio_7,
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inout dgpio_8,
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inout dgpio_9,
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inout dgpio_10,
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inout dgpio_11,
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inout gp_int,
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inout mode,
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inout reset_trx,
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input rx1_dclk_in_n,
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input rx1_dclk_in_p,
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output rx1_enable,
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input rx1_idata_in_n,
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input rx1_idata_in_p,
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input rx1_qdata_in_n,
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input rx1_qdata_in_p,
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input rx1_strobe_in_n,
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input rx1_strobe_in_p,
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input rx2_dclk_in_n,
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input rx2_dclk_in_p,
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output rx2_enable,
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input rx2_idata_in_n,
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input rx2_idata_in_p,
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input rx2_qdata_in_n,
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input rx2_qdata_in_p,
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input rx2_strobe_in_n,
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input rx2_strobe_in_p,
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output tx1_dclk_out_n,
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output tx1_dclk_out_p,
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input tx1_dclk_in_n,
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input tx1_dclk_in_p,
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output tx1_enable,
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output tx1_idata_out_n,
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output tx1_idata_out_p,
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output tx1_qdata_out_n,
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output tx1_qdata_out_p,
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output tx1_strobe_out_n,
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output tx1_strobe_out_p,
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output tx2_dclk_out_n,
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output tx2_dclk_out_p,
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input tx2_dclk_in_n,
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input tx2_dclk_in_p,
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output tx2_enable,
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output tx2_idata_out_n,
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output tx2_idata_out_p,
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output tx2_qdata_out_n,
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output tx2_qdata_out_p,
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output tx2_strobe_out_n,
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output tx2_strobe_out_p,
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inout sm_fan_tach,
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input vadj_err,
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output platform_status,
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inout tdd_sync
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);
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// internal registers
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// internal signals
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wire [63:0] gpio_i;
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wire [63:0] gpio_o;
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wire [63:0] gpio_t;
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wire gpio_rx1_enable_in;
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wire gpio_rx2_enable_in;
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wire gpio_tx1_enable_in;
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wire gpio_tx2_enable_in;
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wire [ 1:0] iic_mux_scl_i_s;
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wire [ 1:0] iic_mux_scl_o_s;
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wire iic_mux_scl_t_s;
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wire [ 1:0] iic_mux_sda_i_s;
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wire [ 1:0] iic_mux_sda_o_s;
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wire iic_mux_sda_t_s;
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wire spi_clk_s;
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wire spi_en_s;
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wire spi_dio_s;
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wire rx1_enable_s;
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wire rx2_enable_s;
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wire tx1_enable_s;
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wire tx2_enable_s;
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wire tdd_sync_loc;
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wire tdd_sync_i;
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wire tdd_sync_cntr;
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// instantiations
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// multi-ssi synchronization
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//
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assign mssi_sync = gpio_o[54];
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assign platform_status = vadj_err;
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ad_iobuf #(
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.DATA_WIDTH(32)
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) i_iobuf_carrier (
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.dio_t(gpio_t[31:0]),
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.dio_i(gpio_o[31:0]),
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.dio_o(gpio_i[31:0]),
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.dio_p(gpio_bd));
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ad_iobuf #(.DATA_WIDTH(16)) i_iobuf (
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.dio_t (vadj_err ? {16{1'b1}} : gpio_t[47:32]),
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.dio_i ({gpio_o[47:32]}),
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.dio_o ({gpio_i[47:32]}),
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.dio_p ({sm_fan_tach, // 47
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reset_trx, // 46
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mode, // 45
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gp_int, // 44
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dgpio_11, // 43
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dgpio_10, // 42
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dgpio_9, // 41
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dgpio_8, // 40
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dgpio_7, // 39
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dgpio_6, // 38
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dgpio_5, // 37
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dgpio_4, // 36
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dgpio_3, // 35
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dgpio_2, // 34
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dgpio_1, // 33
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dgpio_0 })); // 32
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assign gpio_rx1_enable_in = gpio_o[48];
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assign gpio_rx2_enable_in = gpio_o[49];
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assign gpio_tx1_enable_in = gpio_o[50];
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assign gpio_tx2_enable_in = gpio_o[51];
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assign gpio_i[54:48] = gpio_o[54:48];
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assign gpio_i[55] = vadj_err;
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assign gpio_i[63:56] = gpio_o[63:56];
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assign tdd_sync_loc = gpio_o[56];
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// tdd_sync_loc - local sync signal from a GPIO or other source
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// tdd_sync - external sync
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assign tdd_sync_i = tdd_sync_cntr ? tdd_sync_loc : tdd_sync;
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assign tdd_sync = tdd_sync_cntr ? tdd_sync_loc : 1'bz;
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ad_iobuf #(.DATA_WIDTH(2)) i_iobuf_iic_scl (
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.dio_t ({iic_mux_scl_t_s,iic_mux_scl_t_s}),
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.dio_i (iic_mux_scl_o_s),
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.dio_o (iic_mux_scl_i_s),
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.dio_p (iic_mux_scl));
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ad_iobuf #(.DATA_WIDTH(2)) i_iobuf_iic_sda (
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.dio_t ({iic_mux_sda_t_s,iic_mux_sda_t_s}),
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.dio_i (iic_mux_sda_o_s),
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.dio_o (iic_mux_sda_i_s),
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.dio_p (iic_mux_sda));
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system_wrapper i_system_wrapper (
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.ddr_addr (ddr_addr),
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.ddr_ba (ddr_ba),
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.ddr_cas_n (ddr_cas_n),
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.ddr_ck_n (ddr_ck_n),
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.ddr_ck_p (ddr_ck_p),
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.ddr_cke (ddr_cke),
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.ddr_cs_n (ddr_cs_n),
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.ddr_dm (ddr_dm),
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.ddr_dq (ddr_dq),
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.ddr_dqs_n (ddr_dqs_n),
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.ddr_dqs_p (ddr_dqs_p),
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.ddr_odt (ddr_odt),
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.ddr_ras_n (ddr_ras_n),
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.ddr_reset_n (ddr_reset_n),
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.ddr_we_n (ddr_we_n),
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.fixed_io_ddr_vrn (fixed_io_ddr_vrn),
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.fixed_io_ddr_vrp (fixed_io_ddr_vrp),
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.fixed_io_mio (fixed_io_mio),
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.fixed_io_ps_clk (fixed_io_ps_clk),
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.fixed_io_ps_porb (fixed_io_ps_porb),
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.fixed_io_ps_srstb (fixed_io_ps_srstb),
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.gpio_i (gpio_i),
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.gpio_o (gpio_o),
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.gpio_t (gpio_t),
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.hdmi_data (hdmi_data),
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.hdmi_data_e (hdmi_data_e),
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.hdmi_hsync (hdmi_hsync),
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.hdmi_out_clk (hdmi_out_clk),
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.hdmi_vsync (hdmi_vsync),
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.i2s_bclk (i2s_bclk),
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.i2s_lrclk (i2s_lrclk),
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.i2s_mclk (i2s_mclk),
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.i2s_sdata_in (i2s_sdata_in),
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.i2s_sdata_out (i2s_sdata_out),
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.iic_fmc_scl_io (iic_scl),
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.iic_fmc_sda_io (iic_sda),
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.iic_mux_scl_i (iic_mux_scl_i_s),
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.iic_mux_scl_o (iic_mux_scl_o_s),
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.iic_mux_scl_t (iic_mux_scl_t_s),
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.iic_mux_sda_i (iic_mux_sda_i_s),
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.iic_mux_sda_o (iic_mux_sda_o_s),
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.iic_mux_sda_t (iic_mux_sda_t_s),
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.otg_vbusoc (otg_vbusoc),
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.spdif (spdif),
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//FMC connections
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.ref_clk (1'b0),
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.mssi_sync (mssi_sync),
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.tx_output_enable (~vadj_err),
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.rx1_dclk_in_n (rx1_dclk_in_n),
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.rx1_dclk_in_p (rx1_dclk_in_p),
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.rx1_idata_in_n (rx1_idata_in_n),
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.rx1_idata_in_p (rx1_idata_in_p),
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.rx1_qdata_in_n (rx1_qdata_in_n),
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.rx1_qdata_in_p (rx1_qdata_in_p),
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.rx1_strobe_in_n (rx1_strobe_in_n),
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.rx1_strobe_in_p (rx1_strobe_in_p),
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.rx2_dclk_in_n (rx2_dclk_in_n),
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.rx2_dclk_in_p (rx2_dclk_in_p),
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.rx2_idata_in_n (rx2_idata_in_n),
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.rx2_idata_in_p (rx2_idata_in_p),
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.rx2_qdata_in_n (rx2_qdata_in_n),
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.rx2_qdata_in_p (rx2_qdata_in_p),
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.rx2_strobe_in_n (rx2_strobe_in_n),
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.rx2_strobe_in_p (rx2_strobe_in_p),
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.tx1_dclk_out_n (tx1_dclk_out_n),
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.tx1_dclk_out_p (tx1_dclk_out_p),
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.tx1_dclk_in_n (tx1_dclk_in_n),
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.tx1_dclk_in_p (tx1_dclk_in_p),
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.tx1_idata_out_n (tx1_idata_out_n),
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.tx1_idata_out_p (tx1_idata_out_p),
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.tx1_qdata_out_n (tx1_qdata_out_n),
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.tx1_qdata_out_p (tx1_qdata_out_p),
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.tx1_strobe_out_n (tx1_strobe_out_n),
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.tx1_strobe_out_p (tx1_strobe_out_p),
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.tx2_dclk_out_n (tx2_dclk_out_n),
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.tx2_dclk_out_p (tx2_dclk_out_p),
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.tx2_dclk_in_n (tx2_dclk_in_n),
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.tx2_dclk_in_p (tx2_dclk_in_p),
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.tx2_idata_out_n (tx2_idata_out_n),
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.tx2_idata_out_p (tx2_idata_out_p),
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.tx2_qdata_out_n (tx2_qdata_out_n),
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.tx2_qdata_out_p (tx2_qdata_out_p),
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.tx2_strobe_out_n (tx2_strobe_out_n),
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.tx2_strobe_out_p (tx2_strobe_out_p),
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.rx1_enable (rx1_enable_s),
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.rx2_enable (rx2_enable_s),
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.tx1_enable (tx1_enable_s),
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.tx2_enable (tx2_enable_s),
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.gpio_rx1_enable_in (gpio_rx1_enable_in),
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.gpio_rx2_enable_in (gpio_rx2_enable_in),
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.gpio_tx1_enable_in (gpio_tx1_enable_in),
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.gpio_tx2_enable_in (gpio_tx2_enable_in),
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.tdd_sync (tdd_sync_i),
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.tdd_sync_cntr (tdd_sync_cntr),
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.spi0_clk_i (1'b0),
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.spi0_clk_o (spi_clk_s),
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.spi0_csn_0_o (spi_en_s),
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.spi0_csn_1_o (),
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.spi0_csn_2_o (),
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.spi0_csn_i (1'b1),
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.spi0_sdi_i (spi_do),
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.spi0_sdo_i (1'b0),
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.spi0_sdo_o (spi_dio_s),
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.spi1_clk_i (1'b0),
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.spi1_clk_o (),
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.spi1_csn_0_o (),
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.spi1_csn_1_o (),
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.spi1_csn_2_o (),
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.spi1_csn_i (1'b1),
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.spi1_sdi_i (1'b0),
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.spi1_sdo_i (1'b0),
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.spi1_sdo_o ()
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);
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assign spi_clk = vadj_err ? 1'bz : spi_clk_s;
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assign spi_en = vadj_err ? 1'bz : spi_en_s;
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assign spi_dio = vadj_err ? 1'bz : spi_dio_s;
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assign rx1_enable = vadj_err ? 1'bz : rx1_enable_s;
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assign rx2_enable = vadj_err ? 1'bz : rx2_enable_s;
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assign tx1_enable = vadj_err ? 1'bz : tx1_enable_s;
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assign tx2_enable = vadj_err ? 1'bz : tx2_enable_s;
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endmodule
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// ***************************************************************************
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// ***************************************************************************
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