233 lines
10 KiB
Tcl
233 lines
10 KiB
Tcl
# JESD204B attributes
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set RX_NUM_OF_LANES 4 ; # L
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set RX_NUM_OF_CONVERTERS 2 ; # M
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set RX_SAMPLES_PER_FRAME 1 ; # S
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set RX_SAMPLE_WIDTH 16 ; # N/NP
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set RX_SAMPLES_PER_CHANNEL [expr $RX_NUM_OF_LANES * 32 / ($RX_NUM_OF_CONVERTERS * $RX_SAMPLE_WIDTH)]
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set adc_data_width [expr $RX_SAMPLE_WIDTH * $RX_NUM_OF_CONVERTERS * $RX_SAMPLES_PER_CHANNEL]
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set TX_NUM_OF_LANES 4 ; # L
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set TX_NUM_OF_CONVERTERS 2 ; # M
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set TX_SAMPLES_PER_FRAME 1 ; # S
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set TX_SAMPLE_WIDTH 16 ; # N/NP
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set TX_SAMPLES_PER_CHANNEL [expr $TX_NUM_OF_LANES * 32 / ($TX_NUM_OF_CONVERTERS * $TX_SAMPLE_WIDTH)]
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set dac_fifo_name avl_ad9152_fifo
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set dac_data_width 128
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# ad9152-xcvr
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add_instance ad9152_jesd204 adi_jesd204
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set_instance_parameter_value ad9152_jesd204 {ID} {0}
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set_instance_parameter_value ad9152_jesd204 {TX_OR_RX_N} {1}
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set_instance_parameter_value ad9152_jesd204 {LANE_RATE} {12333.3}
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set_instance_parameter_value ad9152_jesd204 {REFCLK_FREQUENCY} {616.665}
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set_instance_parameter_value ad9152_jesd204 {NUM_OF_LANES} $TX_NUM_OF_LANES
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set_instance_parameter_value ad9152_jesd204 {LANE_MAP} {0 3 1 2}
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add_connection sys_clk.clk ad9152_jesd204.sys_clk
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add_connection sys_clk.clk_reset ad9152_jesd204.sys_resetn
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add_interface tx_ref_clk clock sink
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set_interface_property tx_ref_clk EXPORT_OF ad9152_jesd204.ref_clk
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add_interface tx_serial_data conduit end
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set_interface_property tx_serial_data EXPORT_OF ad9152_jesd204.serial_data
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add_interface tx_sysref conduit end
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set_interface_property tx_sysref EXPORT_OF ad9152_jesd204.sysref
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add_interface tx_sync conduit end
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set_interface_property tx_sync EXPORT_OF ad9152_jesd204.sync
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# ad9152-core
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add_instance axi_ad9152_tpl ad_ip_jesd204_tpl_dac
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set_instance_parameter_value axi_ad9152_tpl {ID} {0}
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set_instance_parameter_value axi_ad9152_tpl {NUM_CHANNELS} $TX_NUM_OF_CONVERTERS
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set_instance_parameter_value axi_ad9152_tpl {NUM_LANES} $TX_NUM_OF_LANES
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set_instance_parameter_value axi_ad9152_tpl {BITS_PER_SAMPLE} $TX_SAMPLE_WIDTH
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set_instance_parameter_value axi_ad9152_tpl {CONVERTER_RESOLUTION} $TX_SAMPLE_WIDTH
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add_connection ad9152_jesd204.link_clk axi_ad9152_tpl.link_clk
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add_connection axi_ad9152_tpl.link_data ad9152_jesd204.link_data
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add_connection sys_clk.clk_reset axi_ad9152_tpl.s_axi_reset
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add_connection sys_clk.clk axi_ad9152_tpl.s_axi_clock
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# ad9152-unpack
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add_instance util_ad9152_upack util_upack2
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set_instance_parameter_value util_ad9152_upack {NUM_OF_CHANNELS} $TX_NUM_OF_CONVERTERS
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set_instance_parameter_value util_ad9152_upack {SAMPLES_PER_CHANNEL} $TX_SAMPLES_PER_CHANNEL
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set_instance_parameter_value util_ad9152_upack {SAMPLE_DATA_WIDTH} $TX_SAMPLE_WIDTH
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set_instance_parameter_value util_ad9152_upack {INTERFACE_TYPE} {1}
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add_connection ad9152_jesd204.link_clk util_ad9152_upack.clk
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add_connection ad9152_jesd204.link_reset util_ad9152_upack.reset
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add_connection axi_ad9152_tpl.dac_ch_0 util_ad9152_upack.dac_ch_0
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add_connection axi_ad9152_tpl.dac_ch_1 util_ad9152_upack.dac_ch_1
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# dac fifo
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ad_dacfifo_create $dac_fifo_name $dac_data_width $dac_data_width $dac_fifo_address_width
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add_interface tx_fifo_bypass conduit end
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set_interface_property tx_fifo_bypass EXPORT_OF avl_ad9152_fifo.if_bypass
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add_connection ad9152_jesd204.link_clk avl_ad9152_fifo.if_dac_clk
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add_connection ad9152_jesd204.link_reset avl_ad9152_fifo.if_dac_rst
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add_connection util_ad9152_upack.if_packed_fifo_rd_en avl_ad9152_fifo.if_dac_valid
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add_connection avl_ad9152_fifo.if_dac_data util_ad9152_upack.if_packed_fifo_rd_data
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add_connection avl_ad9152_fifo.if_dac_dunf axi_ad9152_tpl.if_dac_dunf
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# ad9152-dma
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add_instance axi_ad9152_dma axi_dmac
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set_instance_parameter_value axi_ad9152_dma {DMA_DATA_WIDTH_SRC} {128}
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set_instance_parameter_value axi_ad9152_dma {DMA_DATA_WIDTH_DEST} $dac_data_width
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set_instance_parameter_value axi_ad9152_dma {DMA_2D_TRANSFER} {0}
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set_instance_parameter_value axi_ad9152_dma {SYNC_TRANSFER_START} {0}
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set_instance_parameter_value axi_ad9152_dma {CYCLIC} {1}
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set_instance_parameter_value axi_ad9152_dma {DMA_TYPE_DEST} {1}
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set_instance_parameter_value axi_ad9152_dma {DMA_TYPE_SRC} {0}
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set_instance_parameter_value axi_ad9152_dma {FIFO_SIZE} {16}
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set_instance_parameter_value axi_ad9152_dma {HAS_AXIS_TLAST} {1}
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add_connection sys_clk.clk avl_ad9152_fifo.if_dma_clk
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add_connection sys_clk.clk_reset avl_ad9152_fifo.if_dma_rst
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add_connection sys_clk.clk axi_ad9152_dma.if_m_axis_aclk
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add_connection axi_ad9152_dma.m_axis avl_ad9152_fifo.s_axis
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add_connection axi_ad9152_dma.if_m_axis_xfer_req avl_ad9152_fifo.if_dma_xfer_req
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add_connection sys_clk.clk_reset axi_ad9152_dma.s_axi_reset
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add_connection sys_clk.clk axi_ad9152_dma.s_axi_clock
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add_connection sys_clk.clk_reset axi_ad9152_dma.m_src_axi_reset
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add_connection sys_clk.clk axi_ad9152_dma.m_src_axi_clock
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# ad9680-xcvr
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add_instance ad9680_jesd204 adi_jesd204
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set_instance_parameter_value ad9680_jesd204 {ID} {1}
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set_instance_parameter_value ad9680_jesd204 {TX_OR_RX_N} {0}
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set_instance_parameter_value ad9680_jesd204 {LANE_RATE} {12333.3}
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set_instance_parameter_value ad9680_jesd204 {REFCLK_FREQUENCY} {616.665}
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set_instance_parameter_value ad9680_jesd204 {NUM_OF_LANES} {4}
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set_instance_parameter_value ad9680_jesd204 {INPUT_PIPELINE_STAGES} {1}
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add_connection sys_clk.clk ad9680_jesd204.sys_clk
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add_connection sys_clk.clk_reset ad9680_jesd204.sys_resetn
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add_interface rx_ref_clk clock sink
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set_interface_property rx_ref_clk EXPORT_OF ad9680_jesd204.ref_clk
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add_interface rx_serial_data conduit end
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set_interface_property rx_serial_data EXPORT_OF ad9680_jesd204.serial_data
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add_interface rx_sysref conduit end
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set_interface_property rx_sysref EXPORT_OF ad9680_jesd204.sysref
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add_interface rx_sync conduit end
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set_interface_property rx_sync EXPORT_OF ad9680_jesd204.sync
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# ad9680
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add_instance axi_ad9680_tpl ad_ip_jesd204_tpl_adc
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set_instance_parameter_value axi_ad9680_tpl {ID} {0}
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set_instance_parameter_value axi_ad9680_tpl {NUM_CHANNELS} $RX_NUM_OF_CONVERTERS
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set_instance_parameter_value axi_ad9680_tpl {NUM_LANES} $RX_NUM_OF_LANES
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set_instance_parameter_value axi_ad9680_tpl {BITS_PER_SAMPLE} $RX_SAMPLE_WIDTH
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set_instance_parameter_value axi_ad9680_tpl {CONVERTER_RESOLUTION} {14}
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set_instance_parameter_value axi_ad9680_tpl {TWOS_COMPLEMENT} {0}
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add_connection ad9680_jesd204.link_clk axi_ad9680_tpl.link_clk
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add_connection ad9680_jesd204.link_sof axi_ad9680_tpl.if_link_sof
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add_connection ad9680_jesd204.link_data axi_ad9680_tpl.link_data
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add_connection sys_clk.clk_reset axi_ad9680_tpl.s_axi_reset
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add_connection sys_clk.clk axi_ad9680_tpl.s_axi_clock
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# ad9680-pack
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add_instance util_ad9680_cpack util_cpack2
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set_instance_parameter_value util_ad9680_cpack {NUM_OF_CHANNELS} $RX_NUM_OF_CONVERTERS
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set_instance_parameter_value util_ad9680_cpack {SAMPLES_PER_CHANNEL} $RX_NUM_OF_LANES
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set_instance_parameter_value util_ad9680_cpack {SAMPLE_DATA_WIDTH} $RX_SAMPLE_WIDTH
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add_connection ad9680_jesd204.link_clk util_ad9680_cpack.clk
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add_connection ad9680_jesd204.link_reset util_ad9680_cpack.reset
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add_connection axi_ad9680_tpl.adc_ch_0 util_ad9680_cpack.adc_ch_0
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add_connection axi_ad9680_tpl.adc_ch_1 util_ad9680_cpack.adc_ch_1
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# ad9680-fifo
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add_instance ad9680_adcfifo util_adcfifo
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set_instance_parameter_value ad9680_adcfifo {ADC_DATA_WIDTH} $adc_data_width
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set_instance_parameter_value ad9680_adcfifo {DMA_DATA_WIDTH} $adc_data_width
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set_instance_parameter_value ad9680_adcfifo {DMA_ADDRESS_WIDTH} {16}
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add_connection sys_clk.clk_reset ad9680_adcfifo.if_adc_rst
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add_connection ad9680_jesd204.link_clk ad9680_adcfifo.if_adc_clk
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add_connection util_ad9680_cpack.if_packed_fifo_wr_en ad9680_adcfifo.if_adc_wr
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add_connection util_ad9680_cpack.if_packed_fifo_wr_data ad9680_adcfifo.if_adc_wdata
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add_connection sys_clk.clk ad9680_adcfifo.if_dma_clk
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# ad9680-dma
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add_instance axi_ad9680_dma axi_dmac
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set_instance_parameter_value axi_ad9680_dma {DMA_DATA_WIDTH_SRC} $adc_data_width
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set_instance_parameter_value axi_ad9680_dma {DMA_DATA_WIDTH_DEST} {128}
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set_instance_parameter_value axi_ad9680_dma {DMA_LENGTH_WIDTH} {24}
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set_instance_parameter_value axi_ad9680_dma {DMA_2D_TRANSFER} {0}
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set_instance_parameter_value axi_ad9680_dma {SYNC_TRANSFER_START} {0}
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set_instance_parameter_value axi_ad9680_dma {CYCLIC} {0}
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set_instance_parameter_value axi_ad9680_dma {DMA_TYPE_DEST} {0}
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set_instance_parameter_value axi_ad9680_dma {DMA_TYPE_SRC} {1}
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add_connection sys_clk.clk axi_ad9680_dma.if_s_axis_aclk
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add_connection ad9680_adcfifo.m_axis axi_ad9680_dma.s_axis
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add_connection ad9680_adcfifo.if_dma_xfer_req axi_ad9680_dma.if_s_axis_xfer_req
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add_connection ad9680_adcfifo.if_adc_wovf axi_ad9680_tpl.if_adc_dovf
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add_connection sys_clk.clk_reset axi_ad9680_dma.s_axi_reset
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add_connection sys_clk.clk axi_ad9680_dma.s_axi_clock
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add_connection sys_clk.clk_reset axi_ad9680_dma.m_dest_axi_reset
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add_connection sys_clk.clk axi_ad9680_dma.m_dest_axi_clock
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# reconfig sharing
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for {set i 0} {$i < 4} {incr i} {
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add_instance avl_adxcfg_${i} avl_adxcfg
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add_connection sys_clk.clk avl_adxcfg_${i}.rcfg_clk
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add_connection sys_clk.clk_reset avl_adxcfg_${i}.rcfg_reset_n
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add_connection avl_adxcfg_${i}.rcfg_m0 ad9152_jesd204.phy_reconfig_${i}
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add_connection avl_adxcfg_${i}.rcfg_m1 ad9680_jesd204.phy_reconfig_${i}
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}
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# addresses
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ad_cpu_interconnect 0x00400000 ad9152_jesd204.link_reconfig
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ad_cpu_interconnect 0x00424000 ad9152_jesd204.link_management
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ad_cpu_interconnect 0x00425000 ad9152_jesd204.link_pll_reconfig
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ad_cpu_interconnect 0x00426000 ad9152_jesd204.lane_pll_reconfig
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ad_cpu_interconnect 0x00428000 avl_adxcfg_0.rcfg_s0
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ad_cpu_interconnect 0x00429000 avl_adxcfg_1.rcfg_s0
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ad_cpu_interconnect 0x0042a000 avl_adxcfg_2.rcfg_s0
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ad_cpu_interconnect 0x0042b000 avl_adxcfg_3.rcfg_s0
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ad_cpu_interconnect 0x0042c000 axi_ad9152_dma.s_axi
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ad_cpu_interconnect 0x00434000 axi_ad9152_tpl.s_axi
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ad_cpu_interconnect 0x00440000 ad9680_jesd204.link_reconfig
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ad_cpu_interconnect 0x00444000 ad9680_jesd204.link_management
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ad_cpu_interconnect 0x00445000 ad9680_jesd204.link_pll_reconfig
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ad_cpu_interconnect 0x00448000 avl_adxcfg_0.rcfg_s1
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ad_cpu_interconnect 0x00449000 avl_adxcfg_1.rcfg_s1
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ad_cpu_interconnect 0x0044a000 avl_adxcfg_2.rcfg_s1
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ad_cpu_interconnect 0x0044b000 avl_adxcfg_3.rcfg_s1
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ad_cpu_interconnect 0x0044c000 axi_ad9680_dma.s_axi
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ad_cpu_interconnect 0x00450000 axi_ad9680_tpl.s_axi
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# dma interconnects
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ad_dma_interconnect axi_ad9152_dma.m_src_axi
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ad_dma_interconnect axi_ad9680_dma.m_dest_axi
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# interrupts
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ad_cpu_interrupt 8 ad9680_jesd204.interrupt
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ad_cpu_interrupt 9 ad9152_jesd204.interrupt
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ad_cpu_interrupt 10 axi_ad9680_dma.interrupt_sender
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ad_cpu_interrupt 11 axi_ad9152_dma.interrupt_sender
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