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Fix the broken parameters for the following IP cores: axi_i2s_adi, axi_spdif_tx, util_cpack. Make additional name changes on the local parameters. |
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README.md
#HDL Reference Designs
Analog Devices HDL libraries and projects
###Tools version:
- Xilinx : Vivado 2014.4.1
- Altera : Quartus 15.0
###Documentation and support
For first time users, it is highly recommended to go through our HDL user guide.
For support please visit our FPGA Reference Designs Support Community on EngineerZone.