pluto_hdl_adi/projects/fmcadc4/zc706/system_top.v

569 lines
18 KiB
Verilog

// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module system_top (
ddr_addr,
ddr_ba,
ddr_cas_n,
ddr_ck_n,
ddr_ck_p,
ddr_cke,
ddr_cs_n,
ddr_dm,
ddr_dq,
ddr_dqs_n,
ddr_dqs_p,
ddr_odt,
ddr_ras_n,
ddr_reset_n,
ddr_we_n,
fixed_io_ddr_vrn,
fixed_io_ddr_vrp,
fixed_io_mio,
fixed_io_ps_clk,
fixed_io_ps_porb,
fixed_io_ps_srstb,
gpio_bd,
hdmi_out_clk,
hdmi_vsync,
hdmi_hsync,
hdmi_data_e,
hdmi_data,
spdif,
sys_rst,
sys_clk_p,
sys_clk_n,
ddr3_addr,
ddr3_ba,
ddr3_cas_n,
ddr3_ck_n,
ddr3_ck_p,
ddr3_cke,
ddr3_cs_n,
ddr3_dm,
ddr3_dq,
ddr3_dqs_n,
ddr3_dqs_p,
ddr3_odt,
ddr3_ras_n,
ddr3_reset_n,
ddr3_we_n,
iic_scl,
iic_sda,
rx_ref_clk_p,
rx_ref_clk_n,
rx_sysref_p,
rx_sysref_n,
rx_sync_0_p,
rx_sync_0_n,
rx_sync_1_p,
rx_sync_1_n,
rx_data_p,
rx_data_n,
ad9528_rstn,
ad9528_status,
ad9680_1_fda,
ad9680_1_fdb,
ad9680_2_fda,
ad9680_2_fdb,
ad9528_csn,
ada4961_1a_csn,
ada4961_1b_csn,
ad9680_1_csn,
ada4961_2a_csn,
ada4961_2b_csn,
ad9680_2_csn,
spi_clk,
spi_sdio);
inout [14:0] ddr_addr;
inout [ 2:0] ddr_ba;
inout ddr_cas_n;
inout ddr_ck_n;
inout ddr_ck_p;
inout ddr_cke;
inout ddr_cs_n;
inout [ 3:0] ddr_dm;
inout [31:0] ddr_dq;
inout [ 3:0] ddr_dqs_n;
inout [ 3:0] ddr_dqs_p;
inout ddr_odt;
inout ddr_ras_n;
inout ddr_reset_n;
inout ddr_we_n;
inout fixed_io_ddr_vrn;
inout fixed_io_ddr_vrp;
inout [53:0] fixed_io_mio;
inout fixed_io_ps_clk;
inout fixed_io_ps_porb;
inout fixed_io_ps_srstb;
inout [14:0] gpio_bd;
output hdmi_out_clk;
output hdmi_vsync;
output hdmi_hsync;
output hdmi_data_e;
output [23:0] hdmi_data;
output spdif;
input sys_rst;
input sys_clk_p;
input sys_clk_n;
output [13:0] ddr3_addr;
output [ 2:0] ddr3_ba;
output ddr3_cas_n;
output [ 0:0] ddr3_ck_n;
output [ 0:0] ddr3_ck_p;
output [ 0:0] ddr3_cke;
output [ 0:0] ddr3_cs_n;
output [ 7:0] ddr3_dm;
inout [63:0] ddr3_dq;
inout [ 7:0] ddr3_dqs_n;
inout [ 7:0] ddr3_dqs_p;
output [ 0:0] ddr3_odt;
output ddr3_ras_n;
output ddr3_reset_n;
output ddr3_we_n;
inout iic_scl;
inout iic_sda;
input rx_ref_clk_p;
input rx_ref_clk_n;
input rx_sysref_p;
input rx_sysref_n;
output rx_sync_0_p;
output rx_sync_0_n;
output rx_sync_1_p;
output rx_sync_1_n;
input [ 7:0] rx_data_p;
input [ 7:0] rx_data_n;
inout ad9528_rstn;
inout ad9528_status;
inout ad9680_1_fda;
inout ad9680_1_fdb;
inout ad9680_2_fda;
inout ad9680_2_fdb;
output ad9528_csn;
output ada4961_1a_csn;
output ada4961_1b_csn;
output ad9680_1_csn;
output ada4961_2a_csn;
output ada4961_2b_csn;
output ad9680_2_csn;
output spi_clk;
inout spi_sdio;
// internal registers
reg [ 1:0] adc_dcnt = 'd0;
reg adc_dsync = 'd0;
reg adc_dwr = 'd0;
reg [255:0] adc_ddata = 'd0;
// internal signals
wire [63:0] gpio_i;
wire [63:0] gpio_o;
wire [63:0] gpio_t;
wire [ 2:0] spi0_csn;
wire spi0_clk;
wire spi0_mosi;
wire spi0_miso;
wire [ 2:0] spi1_csn;
wire spi1_clk;
wire spi1_mosi;
wire spi1_miso;
wire rx_ref_clk;
wire rx_sysref;
wire rx_sync;
wire adc_clk;
wire [63:0] adc_data_0;
wire [63:0] adc_data_1;
wire [63:0] adc_data_2;
wire [63:0] adc_data_3;
wire adc_enable_0;
wire adc_enable_1;
wire adc_enable_2;
wire adc_enable_3;
wire adc_valid_0;
wire adc_valid_1;
wire adc_valid_2;
wire adc_valid_3;
// adc-pack place holder
always @(posedge adc_clk) begin
adc_dcnt <= adc_dcnt + 1'b1;
case ({adc_enable_3, adc_enable_2, adc_enable_1, adc_enable_0})
4'b1111: begin
adc_dsync <= 1'b1;
adc_dwr <= adc_valid_3 & adc_valid_2 & adc_valid_1 & adc_valid_0;
adc_ddata[255:240] <= $signed(adc_data_3[63:52]);
adc_ddata[239:224] <= $signed(adc_data_2[63:52]);
adc_ddata[223:208] <= $signed(adc_data_1[63:52]);
adc_ddata[207:192] <= $signed(adc_data_0[63:52]);
adc_ddata[191:176] <= $signed(adc_data_3[47:36]);
adc_ddata[175:160] <= $signed(adc_data_2[47:36]);
adc_ddata[159:144] <= $signed(adc_data_1[47:36]);
adc_ddata[143:128] <= $signed(adc_data_0[47:36]);
adc_ddata[127:112] <= $signed(adc_data_3[31:20]);
adc_ddata[111: 96] <= $signed(adc_data_2[31:20]);
adc_ddata[ 95: 80] <= $signed(adc_data_1[31:20]);
adc_ddata[ 79: 64] <= $signed(adc_data_0[31:20]);
adc_ddata[ 63: 48] <= $signed(adc_data_3[15: 4]);
adc_ddata[ 47: 32] <= $signed(adc_data_2[15: 4]);
adc_ddata[ 31: 16] <= $signed(adc_data_1[15: 4]);
adc_ddata[ 15: 0] <= $signed(adc_data_0[15: 4]);
end
4'b0001: begin
adc_dsync <= 1'b1;
adc_dwr <= adc_valid_0 & adc_dcnt[0] & adc_dcnt[1];
adc_ddata[255:240] <= $signed(adc_data_0[63:52]);
adc_ddata[239:224] <= $signed(adc_data_0[47:36]);
adc_ddata[223:208] <= $signed(adc_data_0[31:20]);
adc_ddata[207:192] <= $signed(adc_data_0[15: 4]);
adc_ddata[191:176] <= adc_ddata[255:240];
adc_ddata[175:160] <= adc_ddata[239:224];
adc_ddata[159:144] <= adc_ddata[223:208];
adc_ddata[143:128] <= adc_ddata[207:192];
adc_ddata[127:112] <= adc_ddata[191:176];
adc_ddata[111: 96] <= adc_ddata[175:160];
adc_ddata[ 95: 80] <= adc_ddata[159:144];
adc_ddata[ 79: 64] <= adc_ddata[143:128];
adc_ddata[ 63: 48] <= adc_ddata[127:112];
adc_ddata[ 47: 32] <= adc_ddata[111: 96];
adc_ddata[ 31: 16] <= adc_ddata[ 95: 80];
adc_ddata[ 15: 0] <= adc_ddata[ 79: 64];
end
4'b0010: begin
adc_dsync <= 1'b1;
adc_dwr <= adc_valid_1 & adc_dcnt[0] & adc_dcnt[1];
adc_ddata[255:240] <= $signed(adc_data_1[63:52]);
adc_ddata[239:224] <= $signed(adc_data_1[47:36]);
adc_ddata[223:208] <= $signed(adc_data_1[31:20]);
adc_ddata[207:192] <= $signed(adc_data_1[15: 4]);
adc_ddata[191:176] <= adc_ddata[255:240];
adc_ddata[175:160] <= adc_ddata[239:224];
adc_ddata[159:144] <= adc_ddata[223:208];
adc_ddata[143:128] <= adc_ddata[207:192];
adc_ddata[127:112] <= adc_ddata[191:176];
adc_ddata[111: 96] <= adc_ddata[175:160];
adc_ddata[ 95: 80] <= adc_ddata[159:144];
adc_ddata[ 79: 64] <= adc_ddata[143:128];
adc_ddata[ 63: 48] <= adc_ddata[127:112];
adc_ddata[ 47: 32] <= adc_ddata[111: 96];
adc_ddata[ 31: 16] <= adc_ddata[ 95: 80];
adc_ddata[ 15: 0] <= adc_ddata[ 79: 64];
end
4'b0011: begin
adc_dsync <= 1'b1;
adc_dwr <= adc_valid_1 & adc_valid_0 & adc_dcnt[0];
adc_ddata[255:240] <= $signed(adc_data_1[63:52]);
adc_ddata[239:224] <= $signed(adc_data_0[63:52]);
adc_ddata[223:208] <= $signed(adc_data_1[47:36]);
adc_ddata[207:192] <= $signed(adc_data_0[47:36]);
adc_ddata[191:176] <= $signed(adc_data_1[31:20]);
adc_ddata[175:160] <= $signed(adc_data_0[31:20]);
adc_ddata[159:144] <= $signed(adc_data_1[15: 4]);
adc_ddata[143:128] <= $signed(adc_data_0[15: 4]);
adc_ddata[127:112] <= adc_ddata[255:240];
adc_ddata[111: 96] <= adc_ddata[239:224];
adc_ddata[ 95: 80] <= adc_ddata[223:208];
adc_ddata[ 79: 64] <= adc_ddata[207:192];
adc_ddata[ 63: 48] <= adc_ddata[191:176];
adc_ddata[ 47: 32] <= adc_ddata[175:160];
adc_ddata[ 31: 16] <= adc_ddata[159:144];
adc_ddata[ 15: 0] <= adc_ddata[143:128];
end
4'b0100: begin
adc_dsync <= 1'b1;
adc_dwr <= adc_valid_2 & adc_dcnt[0] & adc_dcnt[1];
adc_ddata[255:240] <= $signed(adc_data_2[63:52]);
adc_ddata[239:224] <= $signed(adc_data_2[47:36]);
adc_ddata[223:208] <= $signed(adc_data_2[31:20]);
adc_ddata[207:192] <= $signed(adc_data_2[15: 4]);
adc_ddata[191:176] <= adc_ddata[255:240];
adc_ddata[175:160] <= adc_ddata[239:224];
adc_ddata[159:144] <= adc_ddata[223:208];
adc_ddata[143:128] <= adc_ddata[207:192];
adc_ddata[127:112] <= adc_ddata[191:176];
adc_ddata[111: 96] <= adc_ddata[175:160];
adc_ddata[ 95: 80] <= adc_ddata[159:144];
adc_ddata[ 79: 64] <= adc_ddata[143:128];
adc_ddata[ 63: 48] <= adc_ddata[127:112];
adc_ddata[ 47: 32] <= adc_ddata[111: 96];
adc_ddata[ 31: 16] <= adc_ddata[ 95: 80];
adc_ddata[ 15: 0] <= adc_ddata[ 79: 64];
end
4'b1000: begin
adc_dsync <= 1'b1;
adc_dwr <= adc_valid_3 & adc_dcnt[0] & adc_dcnt[1];
adc_ddata[255:240] <= $signed(adc_data_3[63:52]);
adc_ddata[239:224] <= $signed(adc_data_3[47:36]);
adc_ddata[223:208] <= $signed(adc_data_3[31:20]);
adc_ddata[207:192] <= $signed(adc_data_3[15: 4]);
adc_ddata[191:176] <= adc_ddata[255:240];
adc_ddata[175:160] <= adc_ddata[239:224];
adc_ddata[159:144] <= adc_ddata[223:208];
adc_ddata[143:128] <= adc_ddata[207:192];
adc_ddata[127:112] <= adc_ddata[191:176];
adc_ddata[111: 96] <= adc_ddata[175:160];
adc_ddata[ 95: 80] <= adc_ddata[159:144];
adc_ddata[ 79: 64] <= adc_ddata[143:128];
adc_ddata[ 63: 48] <= adc_ddata[127:112];
adc_ddata[ 47: 32] <= adc_ddata[111: 96];
adc_ddata[ 31: 16] <= adc_ddata[ 95: 80];
adc_ddata[ 15: 0] <= adc_ddata[ 79: 64];
end
4'b1100: begin
adc_dsync <= 1'b1;
adc_dwr <= adc_valid_3 & adc_valid_2 & adc_dcnt[0];
adc_ddata[255:240] <= $signed(adc_data_3[63:52]);
adc_ddata[239:224] <= $signed(adc_data_2[63:52]);
adc_ddata[223:208] <= $signed(adc_data_3[47:36]);
adc_ddata[207:192] <= $signed(adc_data_2[47:36]);
adc_ddata[191:176] <= $signed(adc_data_3[31:20]);
adc_ddata[175:160] <= $signed(adc_data_2[31:20]);
adc_ddata[159:144] <= $signed(adc_data_3[15: 4]);
adc_ddata[143:128] <= $signed(adc_data_2[15: 4]);
adc_ddata[127:112] <= adc_ddata[255:240];
adc_ddata[111: 96] <= adc_ddata[239:224];
adc_ddata[ 95: 80] <= adc_ddata[223:208];
adc_ddata[ 79: 64] <= adc_ddata[207:192];
adc_ddata[ 63: 48] <= adc_ddata[191:176];
adc_ddata[ 47: 32] <= adc_ddata[175:160];
adc_ddata[ 31: 16] <= adc_ddata[159:144];
adc_ddata[ 15: 0] <= adc_ddata[143:128];
end
default: begin
adc_dsync <= 1'b0;
adc_dwr <= 1'b0;
adc_ddata <= 256'd0;
end
endcase
end
// spi
assign spi_clk = spi0_clk;
assign ad9528_csn = (spi0_csn == 3'b000) ? 1'b0 : 1'b1;
assign ad9680_1_csn = (spi0_csn == 3'b001) ? 1'b0 : 1'b1;
assign ad9680_2_csn = (spi0_csn == 3'b010) ? 1'b0 : 1'b1;
assign ada4961_1a_csn = (spi0_csn == 3'b011) ? 1'b0 : 1'b1;
assign ada4961_1b_csn = (spi0_csn == 3'b100) ? 1'b0 : 1'b1;
assign ada4961_1c_csn = (spi0_csn == 3'b101) ? 1'b0 : 1'b1;
assign ada4961_1d_csn = (spi0_csn == 3'b110) ? 1'b0 : 1'b1;
// instantiations
IBUFDS_GTE2 i_ibufds_rx_ref_clk (
.CEB (1'd0),
.I (rx_ref_clk_p),
.IB (rx_ref_clk_n),
.O (rx_ref_clk),
.ODIV2 ());
IBUFDS i_ibufds_rx_sysref (
.I (rx_sysref_p),
.IB (rx_sysref_n),
.O (rx_sysref));
OBUFDS i_obufds_rx_sync_0 (
.I (rx_sync),
.O (rx_sync_0_p),
.OB (rx_sync_0_n));
OBUFDS i_obufds_rx_sync_1 (
.I (rx_sync),
.O (rx_sync_1_p),
.OB (rx_sync_1_n));
fmcadc4_spi i_spi (
.spi_csn (spi0_csn),
.spi_clk (spi_clk),
.spi_mosi (spi0_mosi),
.spi_miso (spi0_miso),
.spi_sdio (spi_sdio));
ad_iobuf #(.DATA_WIDTH(6)) i_iobuf (
.dio_t (gpio_t[37:32]),
.dio_i (gpio_o[37:32]),
.dio_o (gpio_i[37:32]),
.dio_p ({ ad9680_2_fdb, // 37
ad9680_2_fda, // 36
ad9680_1_fdb, // 35
ad9680_1_fda, // 34
ad9528_status, // 33
ad9528_rstn})); // 32
ad_iobuf #(.DATA_WIDTH(15)) i_iobuf_bd (
.dio_t (gpio_t[14:0]),
.dio_i (gpio_o[14:0]),
.dio_o (gpio_i[14:0]),
.dio_p (gpio_bd));
system_wrapper i_system_wrapper (
.adc_clk (adc_clk),
.adc_data_0 (adc_data_0),
.adc_data_1 (adc_data_1),
.adc_data_2 (adc_data_2),
.adc_data_3 (adc_data_3),
.adc_ddata (adc_ddata),
.adc_dsync (adc_dsync),
.adc_dwr (adc_dwr),
.adc_enable_0 (adc_enable_0),
.adc_enable_1 (adc_enable_1),
.adc_enable_2 (adc_enable_2),
.adc_enable_3 (adc_enable_3),
.adc_valid_0 (adc_valid_0),
.adc_valid_1 (adc_valid_1),
.adc_valid_2 (adc_valid_2),
.adc_valid_3 (adc_valid_3),
.ddr3_addr (ddr3_addr),
.ddr3_ba (ddr3_ba),
.ddr3_cas_n (ddr3_cas_n),
.ddr3_ck_n (ddr3_ck_n),
.ddr3_ck_p (ddr3_ck_p),
.ddr3_cke (ddr3_cke),
.ddr3_cs_n (ddr3_cs_n),
.ddr3_dm (ddr3_dm),
.ddr3_dq (ddr3_dq),
.ddr3_dqs_n (ddr3_dqs_n),
.ddr3_dqs_p (ddr3_dqs_p),
.ddr3_odt (ddr3_odt),
.ddr3_ras_n (ddr3_ras_n),
.ddr3_reset_n (ddr3_reset_n),
.ddr3_we_n (ddr3_we_n),
.ddr_addr (ddr_addr),
.ddr_ba (ddr_ba),
.ddr_cas_n (ddr_cas_n),
.ddr_ck_n (ddr_ck_n),
.ddr_ck_p (ddr_ck_p),
.ddr_cke (ddr_cke),
.ddr_cs_n (ddr_cs_n),
.ddr_dm (ddr_dm),
.ddr_dq (ddr_dq),
.ddr_dqs_n (ddr_dqs_n),
.ddr_dqs_p (ddr_dqs_p),
.ddr_odt (ddr_odt),
.ddr_ras_n (ddr_ras_n),
.ddr_reset_n (ddr_reset_n),
.ddr_we_n (ddr_we_n),
.fixed_io_ddr_vrn (fixed_io_ddr_vrn),
.fixed_io_ddr_vrp (fixed_io_ddr_vrp),
.fixed_io_mio (fixed_io_mio),
.fixed_io_ps_clk (fixed_io_ps_clk),
.fixed_io_ps_porb (fixed_io_ps_porb),
.fixed_io_ps_srstb (fixed_io_ps_srstb),
.gpio_i (gpio_i),
.gpio_o (gpio_o),
.gpio_t (gpio_t),
.hdmi_data (hdmi_data),
.hdmi_data_e (hdmi_data_e),
.hdmi_hsync (hdmi_hsync),
.hdmi_out_clk (hdmi_out_clk),
.hdmi_vsync (hdmi_vsync),
.iic_main_scl_io (iic_scl),
.iic_main_sda_io (iic_sda),
.ps_intr_00 (1'b0),
.ps_intr_01 (1'b0),
.ps_intr_02 (1'b0),
.ps_intr_03 (1'b0),
.ps_intr_04 (1'b0),
.ps_intr_05 (1'b0),
.ps_intr_06 (1'b0),
.ps_intr_07 (1'b0),
.ps_intr_08 (1'b0),
.ps_intr_09 (1'b0),
.ps_intr_10 (1'b0),
.ps_intr_11 (1'b0),
.ps_intr_12 (1'b0),
.rx_data_n (rx_data_n),
.rx_data_p (rx_data_p),
.rx_ref_clk (rx_ref_clk),
.rx_sync (rx_sync),
.rx_sysref (rx_sysref),
.spdif (spdif),
.spi0_clk_i (spi0_clk),
.spi0_clk_o (spi0_clk),
.spi0_csn_0_o (spi0_csn[0]),
.spi0_csn_1_o (spi0_csn[1]),
.spi0_csn_2_o (spi0_csn[2]),
.spi0_csn_i (1'b1),
.spi0_sdi_i (spi0_miso),
.spi0_sdo_i (spi0_mosi),
.spi0_sdo_o (spi0_mosi),
.spi1_clk_i (spi1_clk),
.spi1_clk_o (spi1_clk),
.spi1_csn_0_o (spi1_csn[0]),
.spi1_csn_1_o (spi1_csn[1]),
.spi1_csn_2_o (spi1_csn[2]),
.spi1_csn_i (1'b1),
.spi1_sdi_i (1'b1),
.spi1_sdo_i (spi1_mosi),
.spi1_sdo_o (spi1_mosi),
.sys_clk_clk_n (sys_clk_n),
.sys_clk_clk_p (sys_clk_p),
.sys_rst (sys_rst));
endmodule
// ***************************************************************************
// ***************************************************************************