196 lines
6.5 KiB
ReStructuredText
196 lines
6.5 KiB
ReStructuredText
.. _axi_ad9265:
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AXI AD9265
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================================================================================
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.. hdl-component-diagram::
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The :git-hdl:`AXI AD9265 <library/axi_ad9265>` IP core
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can be used to interface the :adi:`AD9265` ADC, in 1, 2, or 4
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data lines active.
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More about the generic framework interfacing ADCs, that contains the
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``up_adc_channel`` and ``up_adc_common modules``, can be read in :ref:`axi_adc`.
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Features
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--------------------------------------------------------------------------------
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* AXI based configuration
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* CRC validation flag
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* Configurable number of active data lines
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* Real-time data header access
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* Vivado and Quartus compatible
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Files
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.. list-table::
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:header-rows: 1
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* - Name
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- Description
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* - :git-hdl:`library/axi_ad9265/axi_ad9265.v`
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- Verilog source for the AXI AD9265.
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* - :git-hdl:`library/common/up_adc_common.v`
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- Verilog source for the ADC Common regmap.
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* - :git-hdl:`library/common/up_adc_channel.v`
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- Verilog source for the ADC Channel regmap.
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Block Diagram
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--------------------------------------------------------------------------------
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.. image:: block_diagram.svg
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:alt: AXI AD9265 block diagram
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Configuration Parameters
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--------------------------------------------------------------------------------
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.. hdl-parameters::
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* - ID
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- Core ID should be unique for each IP in the system
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* - FPGA_TECHNOLOGY
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- Used to select between devices
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* - ADC_DATAPATH_DISABLE
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- If set, the datapath processing is not generated and output data is
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taken directly from the AD9265
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* - IO_DELAY_GROUP
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- The delay group name which is set for the delay controller
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Interface
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--------------------------------------------------------------------------------
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.. hdl-interfaces::
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* - adc_clk_in_P
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- LVDS input clock
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* - adc_clk_in_n
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- LVDS input clock
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* - adc_data_in_p
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- LVDS input data
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* - adc_data_in_n
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- LVDS input data
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* - adc_or_in_p
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- LVDS input over range
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* - adc_or_in_n
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- LVDS input over range
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* - delay_clk
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- Clock used by the IDELAYCTRL. Connect to 200MHz
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* - adc_clk
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- The input clock is passed through an IBUFGDS and a BUFG primitive and
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adc_clk reults. This is the clock domain that most of the modules of
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the core run on
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* - adc_rst
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- Output reset, on the adc_clk domain
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* - adc_enable
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- Set when the channel is enabled, activated by software
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* - adc_valid
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- Set when valid data is available on the bus
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* - adc_data
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- Data bus
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* - adc_dovf
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- Data overflow input, from the DMA
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* - s_axi
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- Standard AXI Slave Memory Map interface
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Detailed Architecture
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--------------------------------------------------------------------------------
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.. image:: detailed_architecture.svg
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:alt: AXI AD9265 detailed architecture
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Detailed Description
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--------------------------------------------------------------------------------
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The top module, axi_ad9265, instantiates:
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* the lvds interface module
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* the channel processing module
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* the ADC common register map
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* the AXI handling interface
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* delay control module
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The LVDS interface module, axi_ad9265_if, has as input the lvds signals for
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clock, data[7:0] and over range. It uses IO block primitives inside of IP to
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handle the input signals. The input clock is routed to a clock distribution
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primitive from which it drives all the ADC related processing circuitry. The
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data signals are passed through an IDELAYE2 so that each line can be delayed
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independently through the delay controller register map. The IP outputs a data
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value on every clock cycle, along with the over range signal. The latency
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between input and output of the interface module is 3 clock cycles.
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The data from the interface module is processed by the adc channel module.
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The channel module implements:
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* a PRBS monitor
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* data format conversion
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* DC filter
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* the ADC CHANNEL register map
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The data analyzed by the PRBS monitor is raw data received from the interface,
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before being processed in any way. Selection between PN9 and PN23 sequences
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can be done by programming the CHAN_CNTRL_3 register.
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``up_adc_common`` module implements the ADC COMMON register map, allowing for basic
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monitoring and control of the ADC.
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The delay controller module, up_delay_cntrl, allows the dynamic
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reconfiguration of the IDELAYE2 blocks. Changing the delay on each individual
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line helps compensate trace differences between the data lines on the PCB. A
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calibration procedure can be run on software by changing the delays and
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monitoring the PRBS sequence.
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Register Map
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--------------------------------------------------------------------------------
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.. hdl-regmap::
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:name: COMMON
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:no-type-info:
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.. hdl-regmap::
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:name: ADC_COMMON
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:no-type-info:
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.. hdl-regmap::
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:name: ADC_CHANNEL
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:no-type-info:
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Design Guidelines
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--------------------------------------------------------------------------------
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The IP was developed part of the
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:dokuwiki:`AD9265 Native FMC Card Reference Design <resources/fpga/xilinx/fmc/ad9265>`.
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The control of the AD9265 chip is done through a SPI interface, which is needed
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at system level.
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The *ADC interface signals* must be connected directly to the top file of the
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design, as IO primitives are part of the IP.
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The example design uses a DMA to move the data from the output of the IP to
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memory.
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If the data needs to be processed in HDL before moved to the memory, it can be
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done at the output of the IP (at system level) or inside of the adc channel
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module (at IP level).
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The example design uses a processor to program all the registers. If no
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processor is available in your system, you can create your own IP starting from
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the interface module.
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Software Guidelines
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--------------------------------------------------------------------------------
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The software for this IP can be found as part of the AD9265 Native FMC Card
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Reference Design at: :git-no-OS:`projects/ad9265-fmc-125ebz`
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Linux is supported also using :git-linux:`/`.
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References
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-------------------------------------------------------------------------------
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* :git-hdl:`library/axi_ad9265`
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* :adi:`AD9265`
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* :git-linux:`/`
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* :git-no-OS:`projects/ad9265-fmc-125ebz`
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* :dokuwiki:`AD9265 Native FMC Card Reference Design <resources/fpga/xilinx/fmc/ad9265>`
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* :xilinx:`Zynq-7000 SoC Overview <support/documentation/data_sheets/ds190-Zynq-7000-Overview.pdf>`
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* :xilinx:`Zynq-7000 SoC Packaging and Pinout <support/documentation/user_guides/ug865-Zynq-7000-Pkg-Pinout.pdf>`
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