87 lines
3.2 KiB
ReStructuredText
87 lines
3.2 KiB
ReStructuredText
.. _spi_engine execution:
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SPI Engine Execution Module
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================================================================================
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.. hdl-component-diagram::
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The :git-hdl:`SPI Engine Execution <library/spi_engine/spi_engine_execution>`
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IP core is the heart of the SPI Engine framework.
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It is responsible for handling a SPI Engine control stream and translates it
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into low-level SPI bus transactions.
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Files
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-------------------------------------------------------------------------------
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.. list-table::
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:widths: 25 75
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:header-rows: 1
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* - Name
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- Description
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* - :git-hdl:`library/spi_engine/spi_engine_execution/spi_engine_execution.v`
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- Verilog source for the peripheral.
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* - :git-hdl:`library/spi_engine/spi_engine_execution/spi_engine_execution_ip.tcl`
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- TCL script to generate the Vivado IP-integrator project for the peripheral.
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Configuration Parameters
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--------------------------------------------------------------------------------
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.. hdl-parameters::
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* - NUM_OF_CS
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- Number of chip-select signals for the SPI bus (min: 1, max: 8).
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* - DEFAULT_SPI_CFG
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- Reset configuration value for the
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:ref:`spi_engine spi-configuration-register`
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* - DEFAULT_CLK_DIV
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- Reset configuration value for the
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:ref:`spi_engine prescaler-configuration-register`
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* - DATA_WIDTH
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- Data width of the parallel data stream. Will define the transaction's
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granularity. Supported values: 8/16/24/32
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* - NUM_OF_SDI
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- Number of multiple SDI lines, (min: 1, max: 8)
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Signal and Interface Pins
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--------------------------------------------------------------------------------
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.. hdl-interfaces::
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* - clk
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- All other signals are synchronous to this clock.
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* - resetn
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- Resets the internal state machine of the core.
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* - active
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- Indicates whether the peripheral is currently active and processing
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commands.
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* - ctrl
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- :ref:`spi_engine control-interface` subordinate.
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SPI Engine Control stream that contains commands and data for the
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execution module.
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* - spi
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- :ref:`spi_engine spi-bus-interface` controller.
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Low-level SPI bus interface that is controlled by peripheral.
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Theory of Operation
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--------------------------------------------------------------------------------
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The SPI Engine Execution module implements the physical access to the SPI bus.
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It implements a small but powerful programmable state machine that translates a
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SPI Engine command stream into low-level SPI bus access.
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Communication with a command stream generator happens via the ``ctrl``
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interface and the low-level SPI access is handled on the ``spi`` interface.
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The ``active`` signal is asserted as long as the peripheral is busy executing
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incoming commands.
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Internally the SPI Engine execution module consists of an instruction encoder
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that translates the incoming commands into an internal control signal, a
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multi-function counter and compares unit that is responsible for handling the
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timing and a shift register which holds the received and transmitted SPI data.
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The module has an optional programmable pre-scaler register that can be used to
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divide the external clock to the counter and compare unit.
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.. image:: spi_engine.svg
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