148 lines
5.4 KiB
ReStructuredText
148 lines
5.4 KiB
ReStructuredText
.. _util_mii_to_rmii:
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Util MII to RMII
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===============================================================================
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.. hdl-component-diagram::
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The :git-hdl:`Util MII to RMII <library/util_mii_to_rmii>` core
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is designed to interface the Zynq-7000/Zynq UltraScale+ MPSoC - PS
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Gigabit Ethernet MAC and Reduced Media Independent Interface (RMII)
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:adi:`ADIN1300` PHY from the :adi:`CN0506` Dual PHY Ethernet evaluation board.
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Features
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--------------------------------------------------------------------------------
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* Configurable interface for the MAC block (Media Independent Interface - MII
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or Gigabit Media Independent Interface - GMII).
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* Configurable data rate for the MAC block and PHY chip.
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Files
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--------------------------------------------------------------------------------
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.. list-table::
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:header-rows: 1
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* - Name
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- Description
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* - :git-hdl:`library/util_mii_to_rmii/util_mii_to_rmii.v`
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- Verilog source for the main module made of the MII and RMII interfaces.
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* - :git-hdl:`library/util_mii_to_rmii/mac_phy_link.v`
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- Verilog source for the conversion between RMII PHY chip interface and
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MII MAC block interface.
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* - :git-hdl:`library/util_mii_to_rmii/phy_mac_link.v`
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- Verilog source for the conversion between MII MAC block interface and
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RMII PHY chip interface.
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Block Diagram
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--------------------------------------------------------------------------------
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.. image:: block_diagram.svg
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:alt: Util MII to RMII block diagram
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Configuration Parameters
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--------------------------------------------------------------------------------
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.. hdl-parameters::
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* - INTF_CFG
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- MAC Block Interface Selection
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* - RATE_10_100
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- Data Rate Selection
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Interface
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--------------------------------------------------------------------------------
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.. hdl-interfaces::
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* - MII
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- MAC-PHY Link (MII MAC Block to RMII PHY)
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* - GMII
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- MAC-PHY Link (GMII MAC Block to RMII PHY)
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* - RMII
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- PHY-MAC Link (RMII PHY to MII MAC Block)
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* - ref_clk
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- Reference Clock for MII to RMII IP core
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* - reset_n
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- Active-Low reset for MII to RMII IP core
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Theory of Operation
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--------------------------------------------------------------------------------
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The following timing diagrams illustrate different signal protocols for MII and
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RMII interfaces at data rates of 100 and 10 Mbps.
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Receive Transactions
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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- RMII (PHY) receive transaction at 100 Mbps with no errors and phy_crs_dv
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asserted until the final packet dibit. According to the RMII Specification
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Rev. 1.2, after the assertion of phy_crs_dv, several 00's dibits can precede
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the preamble 01's dibits. The preamble is composed of 28 "01" dibits and the
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start of frame delimiter of 3 "01" dibits and one "11" dibit followed by the
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frame containing 64-1522 bytes:
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.. image:: phy_rec_simple.svg
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:alt: PHY Receive Simple
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- RMII (PHY) receive transaction at 100 Mbps with no errors and phy_crs_dv
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toggling at 25 MHz starting on a nibble boundary and indicates the PHY has
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lost the carrier but has accumulated nibbles to transfer:
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.. image:: d2_phy_rec_tog.svg
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:alt: PHY Receive Toggle
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- At a data rate of 10 Mbps (ref_clk frequency divided by 10), mii_rxd will be
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sampled every :math:`10^{th}` cycle.
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- MII receive transaction converted from RMII (PHY) receive transaction at 100
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Mbps. In the MII mode mii_rx_dv and mii_rxd will be sampled on the falling
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edge of the 25 MHz mii_rx_clk and when mii_rx_dv is de-asserted, mii_rxd will
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present 0b0000 to the Ethernet MAC:
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.. image:: mii_recv.svg
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:alt: ETH MAC Receive
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Transmit Transactions
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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- MII transmit transaction at 100 Mbps. In the MII mode mii_tx_en and mii_txd
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will be sampled on the rising edge of the 25 MHz mii_tx_clk:
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.. image:: mii_transm.svg
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:alt: ETH MAC Transmit
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- In case of errors detection, mii_tx_er will be asserted and mii_txd dibits
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will be "01" for the rest of transmission to RMII interface.
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- At a data rate of 10 Mbps (ref_clk frequency divided by 10), mii_txd will be
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sampled every :math:`10^{th}` cycle.
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- RMII transmit transaction converted from MII transmit transaction at 100
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Mbps. In the RMII mode rmii_tx_en and rmii_txd will be sampled on the rising
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edge of the 50 MHz ref_clk:
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.. image:: rmii_transm.svg
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:alt: PHY Transmit
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Software Support
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--------------------------------------------------------------------------------
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Analog Devices recommends to use the provided software drivers.
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- :dokuwiki:`Analog Devices ADIN1300/ADIN1200 PHY Linux Driver <resources/tools-software/linux-drivers/net-phy/adin>`
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References
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--------------------------------------------------------------------------------
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- :git-hdl:`library/util_mii_to_rmii`
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- :adi:`ADIN1300 PHY Information <adin1300>`
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- :adi:`ADIN1300 PHY Documentation <media/en/technical-documentation/data-sheets/ADIN1300.pdf>`
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- :dokuwiki:`ADIN1300 PHY Linux Driver <resources/tools-software/linux-drivers/net-phy/adin>`
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- :adi:`CN0506 Information <en/design-center/reference-designs/circuits-from-the-lab/cn0506.html>`
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- :adi:`CN0506 Reference Note <media/en/reference-design-documentation/reference-designs/cn0506.pdf>`
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- :dokuwiki:`CN0506 HDL Reference Design <resources/eval/user-guides/circuits-from-the-lab/cn0506/hdl>`
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- :dokuwiki:`CN0506 User Guide <resources/eval/user-guides/circuits-from-the-lab/cn0506>`
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