317 lines
11 KiB
Verilog
Executable File
317 lines
11 KiB
Verilog
Executable File
// ***************************************************************************
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// ***************************************************************************
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// Copyright (C) 2022-2023 Analog Devices, Inc. All rights reserved.
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//
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// In this HDL repository, there are many different and unique modules, consisting
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// of various HDL (Verilog or VHDL) components. The individual modules are
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// developed independently, and may be accompanied by separate and unique license
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// terms.
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//
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// The user should read each of these license terms, and understand the
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// freedoms and responsibilities that he or she has by using this source/core.
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//
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// This core is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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// A PARTICULAR PURPOSE.
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//
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// Redistribution and use of source or resulting binaries, with or without modification
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// of this file, are permitted under one of the following two license terms:
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//
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// 1. The GNU General Public License version 2 as published by the
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// Free Software Foundation, which can be found in the top level directory
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// of this repository (LICENSE_GPL2), and also online at:
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// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
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//
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// OR
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//
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// 2. An ADI specific BSD license, which can be found in the top level directory
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// of this repository (LICENSE_ADIBSD), and also on-line at:
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// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
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// This will allow to generate bit files and not release the source code,
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// as long as it attaches to an ADI device.
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//
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module axi_ad3552r_if (
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input clk_in, // 120MHz
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input reset_in,
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input [31:0] dac_data,
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input dac_data_valid,
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input dac_data_valid_ext,
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output dac_data_ready,
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input [ 7:0] address,
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input [23:0] data_write,
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input sdr_ddr_n,
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input symb_8_16b,
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input transfer_data,
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input stream,
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input external_sync,
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input external_sync_arm,
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output if_busy,
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output sync_ext_device,
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output reg [23:0] data_read,
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// DAC control signals
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output sclk,
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output reg csn,
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input [ 3:0] sdio_i,
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output [ 3:0] sdio_o,
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output sdio_t
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);
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wire transfer_data_s;
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wire start_synced;
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wire [31:0] dac_data_int;
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wire dac_data_valid_synced;
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wire external_sync_s;
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reg [55:0] transfer_reg = 56'h0;
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reg [15:0] counter = 16'h0;
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reg [ 2:0] transfer_state = 0;
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reg [ 2:0] transfer_state_next = 0;
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reg cycle_done = 1'b0;
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reg transfer_step = 1'b0;
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reg sclk_ddr = 1'b0;
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reg full_speed = 1'b0;
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reg transfer_data_d = 1'b0;
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reg transfer_data_dd = 1'b0;
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reg [ 3:0] valid_captured_d = 4'b0;
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reg data_r_wn = 1'b0;
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reg valid_captured = 1'b0;
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reg start_transfer = 1'b0;
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reg if_busy_reg = 1'b0;
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reg dac_data_ready_s = 1'b0;
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reg external_sync_arm_reg = 1'b0;
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reg external_sync_reg = 1'b0;
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localparam [ 2:0] IDLE = 3'h0,
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CS_LOW = 3'h1,
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WRITE_ADDRESS = 3'h2,
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TRANSFER_REGISTER = 3'h3,
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READ_REGISTER = 3'h4,
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STREAM = 3'h5,
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CS_HIGH = 3'h6;
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assign if_busy = if_busy_reg;
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// transform the transfer data rising edge into a pulse
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assign transfer_data_s = transfer_data_d & ~transfer_data_dd;
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// start the data stream transfer after valid has been captured
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assign start_synced = valid_captured_d[1] & start_transfer & stream;
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assign sync_ext_device = start_synced ;
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// use dac_data valid from an external source only if external_sync_arm_reg is 1
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assign dac_data_valid_synced = (external_sync_arm_reg == 1'b1) ? (dac_data_valid & dac_data_valid_ext) : dac_data_valid ;
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assign dac_data_ready = dac_data_ready_s & dac_data_valid_synced;
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assign dac_data_int = dac_data;
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// sync the data only if the synchronizations has been armed in software
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assign external_sync_s = ~external_sync_arm_reg | external_sync_reg;
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always @(posedge clk_in) begin
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if(reset_in == 1'b1) begin
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transfer_data_d <= 'd0;
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transfer_data_dd <= 'd0;
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valid_captured_d <= 4'b0;
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valid_captured <= 1'b0;
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end else begin
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transfer_data_d <= transfer_data;
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transfer_data_dd <= transfer_data_d;
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valid_captured_d <= {valid_captured_d[2:0], valid_captured};
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end
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if(transfer_state == CS_HIGH || stream == 1'b0) begin
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start_transfer <= 1'b0;
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valid_captured <= 1'b0;
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valid_captured_d <= 4'b0;
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end
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// pulse to level conversion
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if(external_sync_arm == 1'b1) begin
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external_sync_arm_reg <= 1'b1;
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end
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if(external_sync == 1'b1) begin
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external_sync_reg <= 1'b1;
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end
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if(transfer_state == CS_HIGH) begin
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external_sync_arm_reg <= 1'b0;
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external_sync_reg <= 1'b0;
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end
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if(dac_data_valid == 1'b1 && start_transfer == 1'b1) begin
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valid_captured <= 1'b1;
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end
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if(transfer_data == 1'b1) begin
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start_transfer <= 1'b1;
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end
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end
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always @(posedge clk_in) begin
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if (reset_in == 1'b1) begin
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transfer_state <= IDLE;
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end else begin
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transfer_state <= transfer_state_next;
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end
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end
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// FSM next state logic
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always @(*) begin
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case (transfer_state)
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IDLE : begin
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// goes in to the next state only if the control is to transfer register or synced transfer(if it's armed in software)
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transfer_state_next = ((transfer_data_s == 1'b1 && stream == 1'b0) || (start_synced == 1'b1 && external_sync_s)) ? CS_LOW : IDLE;
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csn = 1'b1;
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transfer_step = 0;
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cycle_done = 0;
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end
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CS_LOW : begin
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// brings CS down
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// loads all configuration
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// puts data on the SDIO pins
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// needs 5 ns before risedge of the clock
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transfer_state_next = WRITE_ADDRESS;
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csn = 1'b0;
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transfer_step = 0;
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cycle_done = 0;
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end
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WRITE_ADDRESS : begin
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// writes the address
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// it works either at full speed (60 MHz) when streaming or normal
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// speed (15 MHz)
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// full speed - 2 clock cycles
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// half speed 8 clock cycles
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cycle_done = full_speed ? (counter == 16'h3) : (counter == 16'hf);
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transfer_state_next = cycle_done ? (stream ? STREAM : TRANSFER_REGISTER) : WRITE_ADDRESS ;
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csn = 1'b0;
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// in streaming, change data on falledge. On regular transfer, change data on negedge.
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//A single step should be done for 8 bit addressing
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transfer_step = full_speed ? (counter[0]== 1'h1) : ((counter[4:0] == 5'h5));
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end
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TRANSFER_REGISTER : begin
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// always works at 15 MHz
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// can be DDR or SDR
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cycle_done = sdr_ddr_n ? (symb_8_16b ? (counter == 16'h10) : (counter == 16'h20)) :
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(symb_8_16b ? (counter == 16'h09) : (counter == 16'h11));
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transfer_state_next = cycle_done ? CS_HIGH : TRANSFER_REGISTER;
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csn = 1'b0;
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// in DDR mode, change data on falledge
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transfer_step = sdr_ddr_n ? (counter[2:0] == 3'h0) : (counter[1:0] == 2'h0);
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end
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STREAM : begin
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// can be DDR or SDR
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// in DDR mode needs to be make sure the clock and data is shifted by 2 ns
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cycle_done = stream ? (sdr_ddr_n ? (counter == 16'h0f) : (counter == 16'h7)):
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(sdr_ddr_n ? (counter == 16'h10) : (counter == 16'h7));
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transfer_state_next = (stream && external_sync_s) ? STREAM: ((cycle_done || external_sync_s == 1'b0) ? CS_HIGH :STREAM);
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csn = 1'b0;
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transfer_step = sdr_ddr_n ? counter[0] : 1'b1;
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end
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CS_HIGH : begin
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cycle_done = 1'b1;
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transfer_state_next = cycle_done ? IDLE : CS_HIGH;
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csn = 1'b1;
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transfer_step = 0;
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end
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default : begin
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cycle_done = 0;
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transfer_state_next = IDLE;
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csn = 1'b1;
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transfer_step = 0;
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end
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endcase
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end
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// counter is used to time all states
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// depends on number of clock cycles per phase
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always @(posedge clk_in) begin
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if (transfer_state == IDLE || reset_in == 1'b1) begin
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counter <= 'b0;
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end else if (transfer_state == WRITE_ADDRESS | transfer_state == TRANSFER_REGISTER | transfer_state == STREAM) begin
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if (cycle_done) begin
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counter <= 0;
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end else begin
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counter <= counter + 1;
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end
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end
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end
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always @(negedge clk_in) begin
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if (transfer_state == STREAM | transfer_state == WRITE_ADDRESS) begin
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sclk_ddr <= !sclk_ddr;
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end else begin
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sclk_ddr <= 0;
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end
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end
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// selection between 60 MHz and 15 MHz
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assign sclk = full_speed ? (sdr_ddr_n ? counter[0] : sclk_ddr) : counter[2];
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always @(posedge clk_in) begin
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if (transfer_state == CS_LOW) begin
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data_r_wn <= address[7];
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end else if (transfer_state == CS_HIGH) begin
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data_r_wn <=1'b0;
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end
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if (transfer_state == STREAM) begin
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if (cycle_done == 1'b1) begin
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dac_data_ready_s <= stream;
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end else begin
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dac_data_ready_s <= 1'b0;
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end
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end else begin
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dac_data_ready_s <= 1'b0;
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end
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if (transfer_state == CS_LOW) begin
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full_speed = stream;
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if(stream) begin
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transfer_reg <= {address,dac_data_int, 16'h0};
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end else begin
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transfer_reg <= {address,data_write, 24'h0};
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end
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end else if ((transfer_state == STREAM & cycle_done) || (transfer_state != STREAM && transfer_state_next == STREAM)) begin
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transfer_reg <= {dac_data_int, 24'h0};
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end else if (transfer_step && transfer_state != CS_HIGH) begin
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transfer_reg <= {transfer_reg[51:0], sdio_i};
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end
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if (transfer_state == CS_HIGH) begin
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if (symb_8_16b == 1'b0) begin
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data_read <= {8'h0,transfer_reg[15:0]};
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end else begin
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data_read <= {16'h0,transfer_reg[7:0]};
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end
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end else begin
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data_read <= data_read;
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end
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if (transfer_state == CS_HIGH || transfer_state == IDLE) begin
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if_busy_reg <= 1'b0;
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end else begin
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if_busy_reg <= 1'b1;
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end
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end
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// address[7] is r_wn : depends also on the state machine, input only when
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// in TRANSFER register mode
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assign sdio_t = (data_r_wn & transfer_state == TRANSFER_REGISTER);
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assign sdio_o = transfer_reg[55:52];
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endmodule
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