294 lines
9.8 KiB
Systemverilog
294 lines
9.8 KiB
Systemverilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright (C) 2022-2023 Analog Devices, Inc. All rights reserved.
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//
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// In this HDL repository, there are many different and unique modules, consisting
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// of various HDL (Verilog or VHDL) components. The individual modules are
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// developed independently, and may be accompanied by separate and unique license
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// terms.
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//
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// The user should read each of these license terms, and understand the
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// freedoms and responsibilities that he or she has by using this source/core.
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//
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// This core is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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// A PARTICULAR PURPOSE.
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//
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// Redistribution and use of source or resulting binaries, with or without modification
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// of this file, are permitted under one of the following two license terms:
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//
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// 1. The GNU General Public License version 2 as published by the
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// Free Software Foundation, which can be found in the top level directory
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// of this repository (LICENSE_GPL2), and also online at:
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// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
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//
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// OR
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//
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// 2. An ADI specific BSD license, which can be found in the top level directory
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// of this repository (LICENSE_ADIBSD), and also on-line at:
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// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
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// This will allow to generate bit files and not release the source code,
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// as long as it attaches to an ADI device.
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//
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/1ps
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module axi_tdd #(
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// Peripheral ID
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parameter ID = 0,
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// Number of active channels
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parameter CHANNEL_COUNT = 8,
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// Default polarity per channel
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parameter DEFAULT_POLARITY = 8'h00,
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// Timing register width, determines how long a single frame can be.
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// T_max = (2^REGISTER_WIDTH) / f_clk
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parameter REGISTER_WIDTH = 32,
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// Burst count register width. Determines the maximum amount of repetitions
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// of a frame.
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parameter BURST_COUNT_WIDTH = 32,
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// Synchronization / triggering options. These are not mutually exclusive, and
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// both internal and external triggering can be available and selected at
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// runtime.
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parameter SYNC_INTERNAL = 1,
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parameter SYNC_EXTERNAL = 0,
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// Whether to insert a CDC stage with false path constraint for the external
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// synchronization input.
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parameter SYNC_EXTERNAL_CDC = 0,
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parameter SYNC_COUNT_WIDTH = 64
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) (
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input logic clk,
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input logic resetn,
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// Sync signal
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input logic sync_in,
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output logic sync_out,
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// Output channels
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output logic [CHANNEL_COUNT-1:0] tdd_channel,
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// AXI BUS
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input logic s_axi_aresetn,
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input logic s_axi_aclk,
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input logic s_axi_awvalid,
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input logic [ 9:0] s_axi_awaddr,
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input logic [ 2:0] s_axi_awprot,
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output logic s_axi_awready,
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input logic s_axi_wvalid,
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input logic [31:0] s_axi_wdata,
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input logic [ 3:0] s_axi_wstrb,
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output logic s_axi_wready,
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output logic s_axi_bvalid,
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output logic [ 1:0] s_axi_bresp,
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input logic s_axi_bready,
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input logic s_axi_arvalid,
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input logic [ 9:0] s_axi_araddr,
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input logic [ 2:0] s_axi_arprot,
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output logic s_axi_arready,
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output logic s_axi_rvalid,
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output logic [ 1:0] s_axi_rresp,
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output logic [31:0] s_axi_rdata,
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input logic s_axi_rready
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);
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// Package import
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import axi_tdd_pkg::*;
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// Internal up bus, translated by up_axi
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logic up_rstn;
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logic up_clk;
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logic up_wreq;
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logic [ 7:0] up_waddr;
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logic [31:0] up_wdata;
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logic up_wack;
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logic up_rreq;
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logic [ 7:0] up_raddr;
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logic [31:0] up_rdata;
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logic up_rack;
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assign up_clk = s_axi_aclk;
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assign up_rstn = s_axi_aresetn;
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// Control signals
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logic tdd_enable;
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logic tdd_sync_rst;
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logic tdd_sync_int;
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logic tdd_sync_ext;
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logic tdd_sync_soft;
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// Config wires
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logic [BURST_COUNT_WIDTH-1:0] asy_tdd_burst_count;
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logic [REGISTER_WIDTH-1:0] asy_tdd_startup_delay;
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logic [REGISTER_WIDTH-1:0] asy_tdd_frame_length;
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// Synchronization config
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logic [SYNC_COUNT_WIDTH-1:0] asy_tdd_sync_period;
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// Channel config
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logic [CHANNEL_COUNT-1:0] tdd_channel_en;
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logic [CHANNEL_COUNT-1:0] asy_tdd_channel_pol;
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logic [REGISTER_WIDTH-1:0] asy_tdd_channel_on [0:CHANNEL_COUNT-1];
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logic [REGISTER_WIDTH-1:0] asy_tdd_channel_off [0:CHANNEL_COUNT-1];
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// Current counter value
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logic [REGISTER_WIDTH-1:0] tdd_counter;
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// Current FSM state
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state_t tdd_cstate;
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// Asserted to indicate the end of a tdd frame. This allows the channels to
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// reset outputs which are still open due to a potential misconfiguration.
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logic tdd_endof_frame;
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axi_tdd_regmap #(
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.ID (ID),
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.CHANNEL_COUNT (CHANNEL_COUNT),
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.DEFAULT_POLARITY (DEFAULT_POLARITY),
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.REGISTER_WIDTH (REGISTER_WIDTH),
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.BURST_COUNT_WIDTH (BURST_COUNT_WIDTH),
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.SYNC_INTERNAL (SYNC_INTERNAL),
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.SYNC_EXTERNAL (SYNC_EXTERNAL),
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.SYNC_EXTERNAL_CDC (SYNC_EXTERNAL_CDC),
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.SYNC_COUNT_WIDTH (SYNC_COUNT_WIDTH)
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) i_regmap (
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.up_rstn (up_rstn),
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.up_clk (up_clk),
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.up_wreq (up_wreq),
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.up_waddr (up_waddr),
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.up_wdata (up_wdata),
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.up_wack (up_wack),
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.up_rreq (up_rreq),
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.up_raddr (up_raddr),
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.up_rdata (up_rdata),
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.up_rack (up_rack),
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.tdd_clk (clk),
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.tdd_resetn (resetn),
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.tdd_cstate (tdd_cstate),
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.tdd_enable (tdd_enable),
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.tdd_channel_en (tdd_channel_en),
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.asy_tdd_channel_pol (asy_tdd_channel_pol),
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.asy_tdd_burst_count (asy_tdd_burst_count),
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.asy_tdd_startup_delay (asy_tdd_startup_delay),
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.asy_tdd_frame_length (asy_tdd_frame_length),
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.asy_tdd_channel_on (asy_tdd_channel_on),
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.asy_tdd_channel_off (asy_tdd_channel_off),
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.asy_tdd_sync_period (asy_tdd_sync_period),
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.tdd_sync_rst (tdd_sync_rst),
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.tdd_sync_int (tdd_sync_int),
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.tdd_sync_ext (tdd_sync_ext),
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.tdd_sync_soft (tdd_sync_soft));
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axi_tdd_counter #(
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.REGISTER_WIDTH (REGISTER_WIDTH),
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.BURST_COUNT_WIDTH (BURST_COUNT_WIDTH)
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) i_counter (
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.clk (clk),
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.resetn (resetn),
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.tdd_enable (tdd_enable),
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.tdd_sync_rst (tdd_sync_rst),
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.tdd_sync (sync_out),
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.asy_tdd_burst_count (asy_tdd_burst_count),
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.asy_tdd_startup_delay (asy_tdd_startup_delay),
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.asy_tdd_frame_length (asy_tdd_frame_length),
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.tdd_counter (tdd_counter),
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.tdd_cstate (tdd_cstate),
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.tdd_endof_frame (tdd_endof_frame));
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axi_tdd_sync_gen #(
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.SYNC_INTERNAL (SYNC_INTERNAL),
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.SYNC_EXTERNAL (SYNC_EXTERNAL),
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.SYNC_EXTERNAL_CDC (SYNC_EXTERNAL_CDC),
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.SYNC_COUNT_WIDTH (SYNC_COUNT_WIDTH)
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) i_sync_gen (
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.clk (clk),
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.resetn (resetn),
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.sync_in (sync_in),
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.sync_out (sync_out),
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.tdd_enable (tdd_enable),
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.tdd_sync_int (tdd_sync_int),
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.tdd_sync_ext (tdd_sync_ext),
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.tdd_sync_soft (tdd_sync_soft),
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.asy_tdd_sync_period (asy_tdd_sync_period));
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genvar i;
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generate
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for (i = 0; i < CHANNEL_COUNT; i=i+1) begin
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axi_tdd_channel #(
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.DEFAULT_POLARITY (DEFAULT_POLARITY[i]),
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.REGISTER_WIDTH (REGISTER_WIDTH)
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) i_channel (
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.clk (clk),
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.resetn (resetn),
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.tdd_counter (tdd_counter),
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.tdd_cstate (tdd_cstate),
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.tdd_enable (tdd_enable),
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.tdd_endof_frame (tdd_endof_frame),
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.ch_en (tdd_channel_en[i]),
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.asy_ch_pol (asy_tdd_channel_pol[i]),
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.asy_t_high (asy_tdd_channel_on[i]),
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.asy_t_low (asy_tdd_channel_off[i]),
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.out (tdd_channel[i]));
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end
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endgenerate
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up_axi #(
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.AXI_ADDRESS_WIDTH(10)
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) i_up_axi (
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.up_rstn(s_axi_aresetn),
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.up_clk(s_axi_aclk),
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.up_axi_awvalid(s_axi_awvalid),
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.up_axi_awaddr(s_axi_awaddr),
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.up_axi_awready(s_axi_awready),
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.up_axi_wvalid(s_axi_wvalid),
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.up_axi_wdata(s_axi_wdata),
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.up_axi_wstrb(s_axi_wstrb),
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.up_axi_wready(s_axi_wready),
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.up_axi_bvalid(s_axi_bvalid),
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.up_axi_bresp(s_axi_bresp),
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.up_axi_bready(s_axi_bready),
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.up_axi_arvalid(s_axi_arvalid),
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.up_axi_araddr(s_axi_araddr),
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.up_axi_arready(s_axi_arready),
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.up_axi_rvalid(s_axi_rvalid),
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.up_axi_rresp(s_axi_rresp),
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.up_axi_rdata(s_axi_rdata),
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.up_axi_rready(s_axi_rready),
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.up_wreq(up_wreq),
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.up_waddr(up_waddr),
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.up_wdata(up_wdata),
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.up_wack(up_wack),
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.up_rreq(up_rreq),
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.up_raddr(up_raddr),
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.up_rdata(up_rdata),
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.up_rack(up_rack));
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endmodule
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