239 lines
8.2 KiB
Verilog
239 lines
8.2 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved.
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//
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// In this HDL repository, there are many different and unique modules, consisting
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// of various HDL (Verilog or VHDL) components. The individual modules are
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// developed independently, and may be accompanied by separate and unique license
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// terms.
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//
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// The user should read each of these license terms, and understand the
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// freedoms and responsibilities that he or she has by using this source/core.
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//
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// This core is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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// A PARTICULAR PURPOSE.
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//
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// Redistribution and use of source or resulting binaries, with or without modification
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// of this file, are permitted under one of the following two license terms:
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//
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// 1. The GNU General Public License version 2 as published by the
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// Free Software Foundation, which can be found in the top level directory
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// of this repository (LICENSE_GPL2), and also online at:
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// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
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//
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// OR
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//
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// 2. An ADI specific BSD license, which can be found in the top level directory
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// of this repository (LICENSE_ADIBSD), and also on-line at:
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// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
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// This will allow to generate bit files and not release the source code,
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// as long as it attaches to an ADI device.
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//
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module up_axi #(
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parameter AXI_ADDRESS_WIDTH = 16
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) (
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// reset and clocks
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input up_rstn,
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input up_clk,
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// axi4 interface
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input up_axi_awvalid,
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input [(AXI_ADDRESS_WIDTH-1):0] up_axi_awaddr,
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output up_axi_awready,
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input up_axi_wvalid,
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input [31:0] up_axi_wdata,
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input [ 3:0] up_axi_wstrb,
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output up_axi_wready,
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output up_axi_bvalid,
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output [ 1:0] up_axi_bresp,
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input up_axi_bready,
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input up_axi_arvalid,
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input [(AXI_ADDRESS_WIDTH-1):0] up_axi_araddr,
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output up_axi_arready,
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output up_axi_rvalid,
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output [ 1:0] up_axi_rresp,
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output [31:0] up_axi_rdata,
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input up_axi_rready,
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// pcore interface
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output up_wreq,
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output [(AXI_ADDRESS_WIDTH-3):0] up_waddr,
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output [31:0] up_wdata,
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input up_wack,
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output up_rreq,
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output [(AXI_ADDRESS_WIDTH-3):0] up_raddr,
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input [31:0] up_rdata,
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input up_rack
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);
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// internal registers
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reg up_axi_awready_int = 'd0;
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reg up_axi_wready_int = 'd0;
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reg up_axi_bvalid_int = 'd0;
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reg up_wack_d = 'd0;
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reg up_wsel = 'd0;
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reg up_wreq_int = 'd0;
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reg [(AXI_ADDRESS_WIDTH-3):0] up_waddr_int = 'd0;
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reg [31:0] up_wdata_int = 'd0;
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reg [ 4:0] up_wcount = 'd0;
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reg up_axi_arready_int = 'd0;
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reg up_axi_rvalid_int = 'd0;
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reg [31:0] up_axi_rdata_int = 'd0;
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reg up_rack_d = 'd0;
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reg [31:0] up_rdata_d = 'd0;
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reg up_rsel = 'd0;
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reg up_rreq_int = 'd0;
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reg [(AXI_ADDRESS_WIDTH-3):0] up_raddr_int = 'd0;
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reg [ 4:0] up_rcount = 'd0;
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// internal signals
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wire up_wack_s;
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wire up_rack_s;
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wire [31:0] up_rdata_s;
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// write channel interface
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assign up_axi_awready = up_axi_awready_int;
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assign up_axi_wready = up_axi_wready_int;
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assign up_axi_bvalid = up_axi_bvalid_int;
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assign up_axi_bresp = 2'd0;
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always @(posedge up_clk) begin
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if (up_rstn == 1'b0) begin
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up_axi_awready_int <= 'd0;
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up_axi_wready_int <= 'd0;
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up_axi_bvalid_int <= 'd0;
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end else begin
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if (up_axi_awready_int == 1'b1) begin
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up_axi_awready_int <= 1'b0;
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end else if (up_wack_s == 1'b1) begin
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up_axi_awready_int <= 1'b1;
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end
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if (up_axi_wready_int == 1'b1) begin
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up_axi_wready_int <= 1'b0;
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end else if (up_wack_s == 1'b1) begin
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up_axi_wready_int <= 1'b1;
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end
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if ((up_axi_bready == 1'b1) && (up_axi_bvalid_int == 1'b1)) begin
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up_axi_bvalid_int <= 1'b0;
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end else if (up_wack_d == 1'b1) begin
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up_axi_bvalid_int <= 1'b1;
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end
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end
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end
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assign up_wreq = up_wreq_int;
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assign up_waddr = up_waddr_int;
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assign up_wdata = up_wdata_int;
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assign up_wack_s = (up_wcount == 5'h1f) ? 1'b1 : (up_wcount[4] & up_wack);
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always @(posedge up_clk) begin
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if (up_rstn == 1'b0) begin
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up_wack_d <= 'd0;
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up_wsel <= 'd0;
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up_wreq_int <= 'd0;
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up_waddr_int <= 'd0;
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up_wdata_int <= 'd0;
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up_wcount <= 'd0;
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end else begin
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up_wack_d <= up_wack_s;
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if (up_wsel == 1'b1) begin
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if ((up_axi_bready == 1'b1) && (up_axi_bvalid_int == 1'b1)) begin
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up_wsel <= 1'b0;
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end
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up_wreq_int <= 1'b0;
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end else begin
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up_wsel <= up_axi_awvalid & up_axi_wvalid;
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up_wreq_int <= up_axi_awvalid & up_axi_wvalid;
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up_waddr_int <= up_axi_awaddr[(AXI_ADDRESS_WIDTH-1):2];
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up_wdata_int <= up_axi_wdata;
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end
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if (up_wack_s == 1'b1) begin
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up_wcount <= 5'h00;
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end else if (up_wcount[4] == 1'b1) begin
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up_wcount <= up_wcount + 1'b1;
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end else if (up_wreq_int == 1'b1) begin
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up_wcount <= 5'h10;
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end
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end
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end
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// read channel interface
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assign up_axi_arready = up_axi_arready_int;
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assign up_axi_rvalid = up_axi_rvalid_int;
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assign up_axi_rdata = up_axi_rdata_int;
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assign up_axi_rresp = 2'd0;
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always @(posedge up_clk) begin
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if (up_rstn == 1'b0) begin
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up_axi_arready_int <= 'd0;
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up_axi_rvalid_int <= 'd0;
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up_axi_rdata_int <= 'd0;
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end else begin
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if (up_axi_arready_int == 1'b1) begin
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up_axi_arready_int <= 1'b0;
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end else if (up_rack_s == 1'b1) begin
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up_axi_arready_int <= 1'b1;
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end
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if ((up_axi_rready == 1'b1) && (up_axi_rvalid_int == 1'b1)) begin
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up_axi_rvalid_int <= 1'b0;
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up_axi_rdata_int <= 32'd0;
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end else if (up_rack_d == 1'b1) begin
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up_axi_rvalid_int <= 1'b1;
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up_axi_rdata_int <= up_rdata_d;
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end
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end
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end
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assign up_rreq = up_rreq_int;
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assign up_raddr = up_raddr_int;
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assign up_rack_s = (up_rcount == 5'h1f) ? 1'b1 : (up_rcount[4] & up_rack);
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assign up_rdata_s = (up_rcount == 5'h1f) ? {2{16'hdead}} : up_rdata;
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always @(posedge up_clk) begin
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if (up_rstn == 1'b0) begin
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up_rack_d <= 'd0;
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up_rdata_d <= 'd0;
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up_rsel <= 'd0;
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up_rreq_int <= 'd0;
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up_raddr_int <= 'd0;
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up_rcount <= 'd0;
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end else begin
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up_rack_d <= up_rack_s;
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up_rdata_d <= up_rdata_s;
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if (up_rsel == 1'b1) begin
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if ((up_axi_rready == 1'b1) && (up_axi_rvalid_int == 1'b1)) begin
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up_rsel <= 1'b0;
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end
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up_rreq_int <= 1'b0;
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end else begin
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up_rsel <= up_axi_arvalid;
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up_rreq_int <= up_axi_arvalid;
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up_raddr_int <= up_axi_araddr[(AXI_ADDRESS_WIDTH-1):2];
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end
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if (up_rack_s == 1'b1) begin
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up_rcount <= 5'h00;
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end else if (up_rcount[4] == 1'b1) begin
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up_rcount <= up_rcount + 1'b1;
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end else if (up_rreq_int == 1'b1) begin
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up_rcount <= 5'h10;
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end
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end
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end
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endmodule
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