665 lines
29 KiB
ReStructuredText
665 lines
29 KiB
ReStructuredText
.. _axi_dmac:
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High-Speed DMA Controller
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================================================================================
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.. symbolator:: ../../../library/axi_dmac/axi_dmac.v
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:caption: axi_dmac
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The AXI DMAC is a high-speed, high-throughput, general purpose DMA controller
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intended to be used to transfer data between system memory and other peripherals
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like high-speed converters.
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Features
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--------------------------------------------------------------------------------
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- Supports multiple interface types
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- AXI3/4 memory mapped
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- AXI4 Streaming
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- ADI FIFO interface
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- Zero-latency transfer switch-over architecture
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- Allows **continuous** high-speed streaming
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- Cyclic transfers
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- 2D transfers
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Utilization
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--------------------------------------------------------------------------------
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.. list-table::
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:header-rows: 1
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* - Device Family
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- LUTs
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- FFs
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* - Intel Arria 10
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- TBD
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- TBD
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* - Xilinx Artix 7
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- TBD
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- TBD
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* - Xilinx Kintex 7
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- TBD
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- TBD
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* - Xilinx Virtex 7
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- TBD
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- TBD
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Files
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--------------------------------------------------------------------------------
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.. list-table::
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:header-rows: 1
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* - Name
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- Description
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* - :git-hdl:`library/axi_dmac/axi_dmac.v`
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- Verilog source for the peripheral.
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Block Diagram
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--------------------------------------------------------------------------------
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.. image:: block_diagram.svg
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:alt: AXI DMAC block diagram
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:align: center
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Configuration Parameters
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--------------------------------------------------------------------------------
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.. hdl-parameters::
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:path: library/axi_dmac
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* - ID
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- Instance identification number.
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* - DMA_DATA_WIDTH_SRC
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- Data path width of the source interface in bits.
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* - DMA_DATA_WIDTH_DEST
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- Data path width of the destination interface in bits.
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* - DMA_LENGTH_WIDTH
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- Width of transfer length control register in bits.
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Limits length of the transfers to 2*\*\ ``DMA_LENGTH_WIDTH``.
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* - DMA_2D_TRANSFER
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- Enable support for 2D transfers.
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* - ASYNC_CLK_REQ_SRC
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- Whether the request and source clock domains are asynchronous.
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* - ASYNC_CLK_SRC_DEST
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- Whether the source and destination clock domains are asynchronous.
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* - ASYNC_CLK_DEST_REQ
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- Whether the destination and request clock domains are asynchronous.
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* - AXI_SLICE_DEST
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- Whether to insert a extra register slice on the source data path.
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* - AXI_SLICE_SRC
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- Whether to insert a extra register slice on the destination data path.
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* - SYNC_TRANSFER_START
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- Enable the transfer start synchronization feature.
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* - CYCLIC
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- Enable support for Cyclic transfers.
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* - DMA_AXI_PROTOCOL_SRC
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- AXI protocol version of the source interface (0 = AXI4, 1 = AXI3).
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* - DMA_AXI_PROTOCOL_DEST
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- AXI protocol version of the destionation interface (0 = AXI4, 1 = AXI3).
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* - DMA_TYPE_SRC
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- Interface type for the source interface
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(0 = AXI-MM, 1 = AXI-Streaming, 2 = ADI-FIFO).
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* - DMA_TYPE_DEST
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- Interface type for the destination interface
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(0 = AXI-MM, 1 = AXI-Streaming, 2 = ADI-FIFO).
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* - DMA_AXI_ADDR_WIDTH
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- Maximum address width for AXI interfaces.
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* - MAX_BYTES_PER_BURST
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- Maximum size of bursts in bytes. Must be power of 2 in a range of 2
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beats to 4096 bytes
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The size of the burst is limited by the largest burst that both source
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and destination supports. This depends on the selected protocol.
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For AXI3 the maximum beats per burst is 16, while for AXI4 is 256. For
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non AXI interfaces the maximum beats per burst is in theory unlimited
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but it is set to 1024 to provide a reasonable upper threshold.
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This limitation is done internally in the core.
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* - FIFO_SIZE
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- Size of the store-and-forward memory in bursts. Size of a burst is
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defined by the ``MAX_BYTES_PER_BURST`` parameter. Must be power of 2 in
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the range of 2 to 32.
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* - DISABLE_DEBUG_REGISTERS
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- Disable debug registers.
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* - ENABLE_DIAGNOSTICS_IF
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- Add insight into internal operation of the core, for debug purposes
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only.
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Interface
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--------------------------------------------------------------------------------
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.. hdl-interfaces::
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* - s_axi_aclk
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- All ``s_axi`` signals and ``irq`` are synchronous to this clock.
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* - s_axi_aresetn
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- Resets the internal state of the peripheral.
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* - s_axi
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- Memory mapped AXI-lite bus that provides access to modules register map.
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* - irq
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- Interrupt output of the module. Is asserted when at least one of the
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modules interrupt is pending and enabled.
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* - m_src_axi_aclk
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- The m_src_axi interface is synchronous to this clock.
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Only present when ``DMA_TYPE_SRC`` parameter is set to AXI-MM (0).
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* - m_src_axi_aresetn
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- Reset for the ``m_src_axi`` interface.
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Only present when ``DMA_TYPE_SRC`` parameter is set to AXI-MM (0).
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* - m_src_axi
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-
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* - m_dest_axi_aclk
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- The ``m_src_axi`` interface is synchronous to this clock.
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Only present when ``DMA_TYPE_DEST`` parameter is set to AXI-MM (0).
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* - m_dest_axi_aresetn
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- Reset for the ``m_dest_axi`` interface.
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Only present when ``DMA_TYPE_DEST`` parameter is set to AXI-MM (0).
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* - m_dest_axi
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-
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* - s_axis_aclk
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- The ``s_axis`` interface is synchronous to this clock.
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Only present when ``DMA_TYPE_SRC`` parameter is set to AXI-Streaming
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(1).
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* - s_axis
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- Only present when ``DMA_TYPE_SRC`` parameter is set to AXI-Streaming
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(1).
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* - m_axis_aclk
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- The ``m_axis`` interface is synchronous to this clock.
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Only present when ``DMA_TYPE_DEST`` parameter is set to AXI-Streaming
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(1).
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* - m_axis
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- Only present when ``DMA_TYPE_DEST`` parameter is set to AXI-Streaming
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(1).
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* - fifo_wr_clk
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- The fifo_wr interface is synchronous to this clock.
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Only present when ``DMA_TYPE_SRC`` parameter is set to FIFO (2).
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* - fifo_wr
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- Only present when ``DMA_TYPE_SRC`` parameter is set to FIFO (2).
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* - fifo_rd_clk
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- The ``fifo_rd`` interface is synchronous to this clock.
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Only present when ``DMA_TYPE_DEST`` parameter is set to FIFO (2).
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* - fifo_rd
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- Only present when ``DMA_TYPE_DEST`` parameter is set to FIFO (2).
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* - dest_diag_level_bursts
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- Only present when ``ENABLE_DIAGNOSTICS_IF`` parameter is set.
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Register Map
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--------------------------------------------------------------------------------
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.. hdl-regmap::
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:name: DMAC
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Theory of Operation
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--------------------------------------------------------------------------------
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HDL Synthesis Settings
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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Sizing of the internal store-and-forward data buffer
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^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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An internal buffer is used to store data from the source interface before it is
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forwarded to the destination once that can accept it. The purpose of the buffer
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is to even out the rate mismatches between the source and destination. e.g if
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the destination is a FIFO interface with a fixed data rate and the source is a
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MM interface, the intent is to keep the buffer as full as possible so in case of
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the MM interface is not ready data can be still provided to the destination
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without risking an underflow. Similarly in case the destination is a MM
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interface and the source a FIFO interface with a fixed data rate, the intent is
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to keep the buffer as empty as possible so in case the MM interface is not ready
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data can be still accepted from the source without risking an overflow.
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The size of the buffer in bytes is determined by the synthesis parameters of the
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module and it is equal to ``FIFO_SIZE`` \* ``MAX_BYTES_PER_BURST``
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The width of the buffer is sized to be the largest width from the source and
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destination interfaces.
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- BUFFER_WIDTH_IN_BYTES =
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MAX(``DMA_DATA_WIDTH_SRC``,\ ``DMA_DATA_WIDTH_DEST``)/8
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- BUFFER_DEPTH = ``FIFO_SIZE``\ \*\ ``MAX_BYTES_PER_BURST`` /
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BUFFER_WIDTH_IN_BYTES
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Interfaces and Signals
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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Register Map Configuration Interface
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^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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The register map configuration interface can be accessed through the AXI4-Lite
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``S_AXI`` interface. The interface is synchronous to the ``s_axi_aclk``. The
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``s_axi_aresetn`` signal is used to reset the peripheral and should be asserted
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during system startup until the ``s_axi_aclk`` is active and stable.
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De-assertion of the reset signal should by synchronous to ``s_axi_aclk``.
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Data Interfaces
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^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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AXI-Streaming slave
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''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''
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The interface back-pressures through the ``s_axis_ready`` signal. If the core is
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in the idle state the ``s_axis_ready`` signal will stay low until a descriptor
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is submitted. The ``s_axis_ready`` will go low once the internal buffer of the
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core is full. It will go high only after enough space is available to store at
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least a burst (``MAX_BYTES_PER_BURST`` bytes); Once the current transfer is
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finished and a new descriptor was not submitted the ``s_axis_ready`` will go
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low. The ``s_axis_ready`` will go low also when the TLAST is used that asserts
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unexpectedly. Unexpectedly means that the transfer length defined by TLAST is
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shorter than the transfer length programmed in the descriptor (``X_LENGTH``
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register). If the next descriptor was already submitted the ``s_axis_ready``
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will assert within few cycles, in other hand will stay low until a new
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descriptor is submitted.
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The ``xfer_req`` is asserted once a transfer is submitted to the descriptor
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queue and stays high until all data from the current transfer is received/send
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through the AXI Stream/FIFO interface. If during the current transfer another
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descriptor is queued (submitted) it will stay high and so on.
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Configuration Interface
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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The peripheral features a register map configuration interface that can be
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accessed through the AXI4-Lite ``S_AXI`` port. The register map can be used to
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configure the peripherals operational parameters, query the current status of
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the device and query the features supported by the device.
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Peripheral Identification
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^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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The peripheral contains multiple registers that allow the identification of the
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peripheral as well as discovery of features that were configured at HDL
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synthesis time. Apart from the ``SCRATCH`` register all registers in this
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section are read only and writes to them will be ignored.
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The ``VERSION`` (``0x000``) register contains the version of the peripheral. The
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version determines the register map layout and general features supported by the
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peripheral. The version number follows `semantic versioning <http://semver.org/>`_.
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Increments in the major number indicate backwards incompatible changes, increments
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in the minor number indicate backwards compatible changes, patch letter increments
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indicate fixed incorrect behavior.
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The ``PERIPHERAL_ID`` (``0x004``) register contains the value of the ``ID`` HDL
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configuration parameter that was set during synthesis. Its primary function is
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to allow to distinguish between multiple instances of the peripheral in the same
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design.
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The ``SCRATCH`` (``0x008``) register is a general purpose 32-bit register that
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can be set to an arbitrary values. Reading the register will yield the value
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previously written (The value will be cleared when the peripheral is reset).
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It's content does not affect the operation of the peripheral. It can be used by
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software to test whether the register map is accessible or store custom
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peripheral associated data.
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The ``IDENTIFICATION`` (``0x00c``) register contains the value of ``"DMAC"``.
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This value is unique to this type of peripheral and can be used to ensure that
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the peripheral exists at the expected location in the memory mapped IO register
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space.
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Interrupt Handling
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^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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Interrupt processing is handled by three closely related registers. All three
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registers follow the same layout, each bit in the register corresponds to one
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particular interrupt.
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When an interrupt event occurs it is recorded in the ``IRQ_SOURCE`` (``0x088``)
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register. For a recorded interrupt event the corresponding bit is set to 1. If
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an interrupt event occurs while the bit is already set to 1 it will stay set to
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1.
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The ``IRQ_MASK`` (``0x080``) register controls how recorded interrupt events
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propagate. An interrupt is considered to be enabled if the corresponding bit in
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the ``IRQ_MASK`` register is set to 0, it is considered to be disabled if the
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bit is set to 1.
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Disabling an interrupt will not prevent it from being recorded, but only its
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propagation. This means if an interrupt event was previously recorded while the
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interrupt was disabled and the interrupt is being enabled the interrupt event
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will then propagate.
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An interrupt event that has been recorded and is enabled propagates to the
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``IRQ_PENDING`` (``0x084``) register. The corresponding bit for such an
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interrupt will read as 1. Disabled or interrupts for which no events have been
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recorded will read as 0. Also if at least one interrupt has been recorded and is
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enabled the external ``irq`` signal will be asserted to signal the IRQ event to
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the upstream IRQ controller.
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A recorded interrupt event can be cleared (or acknowledged) by writing a 1 to
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the corresponding bit to either the ``IRQ_SOURCE`` or ``IRQ_PENDING`` register.
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It is possible to clear multiple interrupt events at the same time by setting
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multiple bits in a single write operation.
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For more details regarding interrupt operation see the :ref:`axi_dmac interrupts`.
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Transfer Configuration
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^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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The ``DEST_ADDRESS`` (``0x410``) register contains the destination address of
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the transfer. The address must be aligned to the destination bus width.
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Non-aligned addresses will be automatically aligned internally by setting the
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LSBs to 0. This register is only valid if the DMA channel has been configured
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for write to memory support.
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The ``SRC_ADDRESS`` (``0x414``) register contains the source address of the
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transfer. The address must be aligned to the source bus width. Non-aligned
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addresses will be automatically aligned internally by setting the LSBs to 0.
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This register is only valid if the DMA channel has been configured for write
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from memory support.
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The ``X_LENGTH`` (``0x418``) register contains the number of bytes to transfer
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per row. The number of bytes is equal to the value of the register + 1 (E.g. a
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value of 0x3ff means 0x400 bytes).
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The ``Y_LENGTH`` (``0x41C``) register contains the number of rows to transfer.
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The number of rows is equal to the value of the register + 1 (E.g. a value of
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1079 means 1080 rows). This register is only valid if the DMA channel has been
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configured with 2D transfer support. If 2D transfer support is disabled the
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number of rows is always 1 per transfer.
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The ``SRC_STRIDE`` (``0x424``) and ``DEST_STRIDE`` (``0x420``) registers contain
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the number of bytes between the start of one row and the next row. Needs to be
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aligned to the bus width. This field is only valid if the DMA channel has been
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configured with 2D transfer support.
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The total number of bytes transferred is equal to (``X_LENGTH`` + ``1``) \*
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(``Y_LENGTH`` + ``1``).
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The ``FLAGS`` (``0x40C``) register controls the behavior of the transfer.
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- If the ``CYCLIC`` (``[0]``) bit is set the transfer will run in
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:ref:`axi_dmac cyclic-transfers`.
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- If the ``TLAST`` (``[1]``) bit is set the TLAST signal will be asserted
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during the last beat of the AXI Stream transfer.
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Transfer Submission
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^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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Writing a 1 to the ``TRANSFER_SUBMIT`` (``0x408``) register queues a new
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transfer. If the internal transfer queue is full the ``TRANSFER_SUBMIT`` bit
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will stay asserted until room becomes available, the bit transitions back to 0
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once the transfer has been queued. Writing a 0 to this register has no effect.
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Writing a 1 to the register while it is already 1 will also have no effect. When
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submitting a new transfer software should always check that the
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``TRANSFER_SUBMIT`` [0] bit is 0 before setting it, otherwise the transfer will
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not be queued.
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If the DMA channel is disabled (``ENABLE`` control bit is set to 0) while a
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queuing operation is in progress it will be aborted and the ``TRANSFER_SUBMIT``
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bit will de-assert.
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The ``TRANSFER_ID`` (``0x404``) register contains the ID of the next transfer.
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The ID is generated by the DMA controller and can be used to check if a transfer
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has been completed by checking the corresponding bit in the ``TRANSFER_DONE``
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(``0x428``) register. The contents of this register is only valid if
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``TRANSFER_SUBMIT`` is 0. Software should read this register before asserting
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the ``TRANSFER_SUBMIT`` bit.
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Transfer Status
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^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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The ``TRANSFER_DONE`` (``0x428``) register indicates whether a submitted
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transfer has been completed. Each bit in the register corresponds to transfer
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ID. When a new transfer is submitted the corresponding bit in the register is
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cleared, once the the transfer has been completed the corresponding bit will be
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set.
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The ``ACTIVE_TRANSFER_ID`` (``0x42C``) register holds the ID of the currently
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active transfer. When no transfer is active the value of register will be equal
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to the value of the ``TRANSFER_ID`` (``0x404``) register.
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Transfer length reporting
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^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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When using MM or FIFO source interfaces the amount of data which the core will
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transfer is defined by ``X_LENGTH`` and ``Y_LENGTH`` registers in the moment of
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the transfer submission. Once the corresponding bit from the ``TRANSFER_DONE``
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is set the programmed amount of data is transferred.
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When using streaming interface (AXIS) as source, the length of transfers will be
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defined by the assertion of ``TLAST`` signal which is unknown at the moment of
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transfer submission. In this case ``X_LENGTH`` and ``Y_LENGTH`` specified during
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the transfer submission will act as upper limits for the transfer. Transfers
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where the TLAST occurs ahead of programmed length will be noted as partial
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transfers. If ``PARTIAL_REPORTING_EN`` bit from the ``FLAGS`` register is set,
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the length of partial transfers will be recorded and exposed through the
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``PARTIAL_TRANSFER_LENGTH`` and ``PARTIAL_TRANSFER_ID`` registers. The
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availability of information regarding partial transfers is done through the
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``PARTIAL_TRANSFER_DONE`` field of ``TRANSFER_DONE`` register.
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During operation the ``TRANSFER_PROGRESS`` register can be consulted to check
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the progress of the current transfer. The register presents the number of bytes
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the destination accepted during the in progress transfer. This register will be
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cleared once the transfer completes. This register should be used for debugging
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purposes only.
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Transfer Tear-down
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^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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Non-cyclic transfers stop once the programmed amount of data is transferred to
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the destination. Cyclic transfers needs to be stopped with software intervention
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by setting the ``ENABLE`` control bit to 0. In case if required, non cyclic
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transfers can be interrupted in the same way. The transfer tear down is done
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gracefully and is done at a burst resolution on MM interfaces and beat
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resolution on non-MM interfaces. DMAC shuts down gracefully as fast as possible
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while completing all in-progress MM transactions.
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Source side: For MM interface once the ``ENABLE`` bit de-asserts the DMAC won't
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issue new requests towards the source interface but will wait until all pending
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requests are fulfilled by the source. For non-MM interfaces, once the ``ENABLE``
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bit de-asserts the DMAC will stop to accept new data. This will lead to partial
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bursts in the internal buffer but this data will be cleared/lost once the
|
||
destination side completes all pending bursts.
|
||
|
||
Destination side: For MM interface the DMAC will complete all pending requests
|
||
that have been started by issuing the address. For non-MM interfaces once the
|
||
``ENABLE`` bit de-asserts the DMAC will stop to drive new data. All the data
|
||
from the internal buffer will be cleared/lost. In case of AXIS the DMAC will
|
||
wait for data to be accepted if valid is high since it can't just de-assert
|
||
valid without breaking the interface semantics
|
||
|
||
.. _axi_dmac interrupts:
|
||
|
||
Interrupts
|
||
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||
|
||
The DMA controller supports interrupts to allow asynchronous notification of
|
||
certain events to the CPU. This can be used as an alternative to busy-polling
|
||
the status registers. Two types of interrupt events are implemented by the DMA
|
||
controller.
|
||
|
||
The ``TRANSFER_QUEUED`` interrupt is asserted when a transfer is moved from the
|
||
register map to the internal transfer queue. This is equivalent to the
|
||
``TRANSFER_SUBMIT`` register transitioning from 1 to 0. Software can use this
|
||
interrupt as an indication that the next transfer can be submitted.
|
||
|
||
Note that a transfer being queued does not mean that it has been started yet. If
|
||
other transfers are already queued those will be processed first.
|
||
|
||
The ``TRANSFER_COMPLETED`` interrupt is asserted when a previously submitted
|
||
transfer has been completed. To find out which transfer has been completed the
|
||
``TRANSFER_DONE`` register should be checked.
|
||
|
||
Note that depending on the transfer size and interrupt latency it is possible
|
||
for multiple transfers to complete before the interrupt handler runs. In that
|
||
case the interrupt handler will only run once. Software should always check all
|
||
submitted transfers for completion.
|
||
|
||
2D Transfers
|
||
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||
|
||
If the ``DMA_2D_TRANSFER`` HDL synthesis configuration parameter is set the DMA
|
||
controller has support for 2D transfers.
|
||
|
||
A 2D transfer is composed of a number of rows with each row containing a certain
|
||
number of bytes. Between each row there might be a certain amount of padding
|
||
bytes that are skipped by the DMA.
|
||
|
||
For 2D transfers the ``X_LENGTH`` register configures the number of bytes per
|
||
row and the ``Y_LENGTH`` register configures the number of rows. The
|
||
``SRC_STRIDE`` and ``DEST_STRIDE`` registers configure the number of bytes in
|
||
between start of two rows.
|
||
|
||
E.g. the first row will start at the configured source or destination address,
|
||
the second row will start at the configured source or destination address plus
|
||
the stride and so on.
|
||
|
||
.. math::
|
||
|
||
ROW\_SRC\_ADDRESS = SRC\_ADDRESS + SRC\_STRIDE * N
|
||
|
||
.. math::
|
||
|
||
ROW\_DEST\_ADDRESS = DEST\_ADDRESS + DEST\_STRIDE * N
|
||
|
||
If support for 2D transfers is disabled only the X_LENGTH register is
|
||
considered and the number of rows per transfer is fixed to 1.
|
||
|
||
.. _axi_dmac cyclic-transfers:
|
||
|
||
Cyclic Transfers
|
||
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||
|
||
If the ``CYCLIC`` HDL synthesis configuration parameter is set the DMA
|
||
controller has support for cyclic transfers.
|
||
|
||
A cyclic transfer once completed will restart automatically with the same
|
||
configuration. The behavior of cyclic transfer is equivalent to submitting the
|
||
same transfer over and over again, but generates less software management
|
||
overhead.
|
||
|
||
A transfer is cyclic if the ``CYCLIC`` (``[0]``) bit of the ``FLAGS``
|
||
(``0x40C``) is set to 1 during transfer submission.
|
||
|
||
For cyclic transfers no end-of-transfer interrupts will be generated. To stop a
|
||
cyclic transfer the DMA channel must be disabled.
|
||
|
||
Any additional transfers that are submitted after the submission of a cyclic
|
||
transfer (and before stopping the cyclic transfer) will never be executed.
|
||
|
||
Transfer Start Synchronization
|
||
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||
|
||
If the transfer start synchronization feature of the DMA controller is enabled
|
||
the start of a transfer is synchronized to a flag in the data stream. This is
|
||
primarily useful if the data stream does not have any back-pressure and one unit
|
||
of data spans multiple beats (e.g. packetized data). This ensures that the data
|
||
is properly aligned to the beginning of the memory buffer.
|
||
|
||
Data that is received before the synchronization flag is asserted will be
|
||
ignored by the DMA controller.
|
||
|
||
For the FIFO write interface the ``fifo_wr_sync`` signal is the synchronization
|
||
flag signal. For the AXI-Streaming interface the synchronization flag is carried
|
||
in ``s_axis_user[0]``. In both cases the synchronization flag is qualified by
|
||
the same control signal as the data.
|
||
|
||
Diagnostics interface
|
||
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||
|
||
For debug purposes a diagnostics interface is added to the core.
|
||
The ``dest_diag_level_bursts`` signal adds insight into the fullness of the
|
||
internal memory buffer during operation. The information is exposed in number
|
||
of bursts where the size of a burst is defined by the ``MAX_BYTES_PER_BURST``
|
||
parameter. The value of ``dest_diag_level_bursts`` increments for each burst
|
||
accumulated in the DMACs internal buffer. It decrements once the burst leaves
|
||
the DMAC on its destination port. The signal is synchronous to the destination
|
||
clock domain (``m_dest_axi_aclk`` or ``m_axis_aclk`` depending on ``DMA_TYPE_DEST``).
|
||
|
||
Limitations
|
||
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||
|
||
AXI 4kByte Address Boundary
|
||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||
|
||
Software must program the ``SRC_ADDRESS`` and ``DEST_ADDRESS`` registers in such
|
||
way that AXI burst won't cross the 4kB address boundary. The following condition
|
||
must hold:
|
||
|
||
* ``MAX_BYTES_PER_BURST`` ≤ 4096;
|
||
* ``MAX_BYTES_PER_BURST`` is power of 2;
|
||
* ``SRC/DEST_ADDRESS`` mod ``MAX_BYTES_PER_BURST`` == 0
|
||
* ``SRC/DEST_ADDRESS[11:0]`` + MIN(``X_LENGTH``\ +1,\ ``MAX_BYTES_PER_BURST``) ≤ 4096
|
||
|
||
Address Alignment
|
||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||
|
||
Software must program the ``SRC_ADDRESS`` and ``DEST_ADDRESS``\ registers to be
|
||
multiple of the corresponding MM data bus. The following conditions must hold:
|
||
|
||
* ``SRC_ADDRESS`` MOD (``DMA_DATA_WIDTH_SRC``/8) == 0
|
||
* ``DEST_ADDRESS`` MOD (``DMA_DATA_WIDTH_DEST``/8) == 0
|
||
|
||
Transfer Length Alignment
|
||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||
|
||
Software must program the ``X_LENGTH`` register to be multiple of the widest
|
||
data bus. The following condition must hold:
|
||
|
||
- (``X_LENGTH``\ +1) MOD MAX(``DMA_DATA_WIDTH_SRC``, ``DMA_DATA_WIDTH_DEST``)/8
|
||
== 0
|
||
|
||
This restriction can be relaxed for the memory mapped interfaces. This is done
|
||
by partially ignoring data of a beat from/to the MM interface:
|
||
|
||
- For write access the strobe bits are used to mask out bytes that do not
|
||
contain valid data.
|
||
- For read access a full beat is read but part of the data is discarded. This
|
||
works fine as long as the read access is side effect free. I.e. this method
|
||
should not be used to access data from memory mapped peripherals like a FIFO.
|
||
|
||
E.g. the length alignment requirement of a DMA configured for a 64-bit memory
|
||
mapped interface and a 16-bit streaming interface is only 2 bytes instead of 8
|
||
bytes.
|
||
|
||
Note that the address alignment requirement is not affected by this. The address
|
||
still needs to be aligned to the width of the MM interface that it belongs to.
|
||
|
||
Software Support
|
||
--------------------------------------------------------------------------------
|
||
|
||
Analog Devices recommends to use the provided software drivers.
|
||
|
||
- :dokuwiki:`Analog Device AXI-DMAC DMA Controller Linux Driver
|
||
<resources/tools-software/linux-drivers/axi-dmac>`
|
||
|
||
Known Issues
|
||
--------------------------------------------------------------------------------
|
||
|
||
1. When max bytes per burst matches the data width of destination interface an
|
||
erroneous extra beat is inserted after every valid beat on the destination side.
|
||
Example configuration:
|
||
|
||
* axi mm -> axi stream
|
||
* max bytes per burst = 128
|
||
* destination width = 1024 bits
|
||
|
||
Workaround: increase the max bytes per burst to larger than 128
|
||
|
||
Technical Support
|
||
--------------------------------------------------------------------------------
|
||
|
||
Analog Devices will provide limited online support for anyone using the core
|
||
with Analog Devices components (ADC, DAC, Video, Audio, etc) via the :ez:`fpga`.
|
||
|
||
Glossary
|
||
--------------------------------------------------------------------------------
|
||
|
||
.. list-table::
|
||
:header-rows: 1
|
||
|
||
* - Term
|
||
- Description
|
||
* - beat
|
||
- Represents the amount of data that is transferred in one clock cycle.
|
||
* - burst
|
||
- Represents the amount of data that is transferred in a group of
|
||
consecutive beats.
|
||
* - partial transfer
|
||
- Represents a transfer which is shorter than the programmed length that
|
||
is based on the X_LENGTH and Y_LENGTH registers. This can occur on AXIS
|
||
source interfaces when TLAST asserts earlier than the programmed
|
||
length.
|