421 lines
13 KiB
Verilog
421 lines
13 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2011(c) Analog Devices, Inc.
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//
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without modification,
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// are permitted provided that the following conditions are met:
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// - Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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// - Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in
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// the documentation and/or other materials provided with the
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// distribution.
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// - Neither the name of Analog Devices, Inc. nor the names of its
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// contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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// - The use of this software may or may not infringe the patent rights
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// of one or more patent holders. This license does not release you
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// from the requirement that you obtain separate licenses from these
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// patent holders to use this software.
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// - Use of the software either in source or binary form, must be run
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// on or directly connected to an Analog Devices Inc. component.
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//
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// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
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// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
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// PARTICULAR PURPOSE ARE DISCLAIMED.
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//
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// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
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// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
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// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module up_dac_common (
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// mmcm reset
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mmcm_rst,
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// dac interface
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dac_clk,
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dac_rst,
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dac_sync,
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dac_frame,
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dac_clksel,
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dac_par_type,
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dac_par_enb,
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dac_r1_mode,
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dac_datafmt,
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dac_datarate,
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dac_status,
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dac_status_ovf,
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dac_status_unf,
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dac_clk_ratio,
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// drp interface
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up_drp_sel,
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up_drp_wr,
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up_drp_addr,
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up_drp_wdata,
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up_drp_rdata,
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up_drp_ready,
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up_drp_locked,
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// user channel control
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up_usr_chanmax,
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dac_usr_chanmax,
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up_dac_gpio_in,
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up_dac_gpio_out,
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// bus interface
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up_rstn,
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up_clk,
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up_wreq,
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up_waddr,
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up_wdata,
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up_wack,
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up_rreq,
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up_raddr,
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up_rdata,
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up_rack);
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// parameters
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localparam PCORE_VERSION = 32'h00080062;
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parameter ID = 0;
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parameter DAC_COMMON_ID = 6'h10;
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// mmcm reset
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output mmcm_rst;
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// dac interface
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input dac_clk;
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output dac_rst;
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output dac_sync;
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output dac_frame;
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output dac_clksel;
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output dac_par_type;
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output dac_par_enb;
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output dac_r1_mode;
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output dac_datafmt;
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output [ 7:0] dac_datarate;
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input dac_status;
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input dac_status_ovf;
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input dac_status_unf;
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input [31:0] dac_clk_ratio;
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// drp interface
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output up_drp_sel;
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output up_drp_wr;
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output [11:0] up_drp_addr;
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output [31:0] up_drp_wdata;
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input [31:0] up_drp_rdata;
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input up_drp_ready;
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input up_drp_locked;
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// user channel control
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output [ 7:0] up_usr_chanmax;
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input [ 7:0] dac_usr_chanmax;
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input [31:0] up_dac_gpio_in;
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output [31:0] up_dac_gpio_out;
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// bus interface
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input up_rstn;
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input up_clk;
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input up_wreq;
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input [13:0] up_waddr;
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input [31:0] up_wdata;
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output up_wack;
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input up_rreq;
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input [13:0] up_raddr;
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output [31:0] up_rdata;
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output up_rack;
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// internal registers
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reg up_core_preset = 'd0;
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reg up_mmcm_preset = 'd0;
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reg up_wack = 'd0;
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reg [31:0] up_scratch = 'd0;
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reg up_mmcm_resetn = 'd0;
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reg up_resetn = 'd0;
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reg up_dac_sync = 'd0;
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reg up_dac_par_type = 'd0;
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reg up_dac_par_enb = 'd0;
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reg up_dac_r1_mode = 'd0;
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reg up_dac_datafmt = 'd0;
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reg [ 7:0] up_dac_datarate = 'd0;
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reg up_dac_frame = 'd0;
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reg up_dac_clksel = 'd0;
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reg up_drp_sel = 'd0;
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reg up_drp_wr = 'd0;
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reg up_drp_status = 'd0;
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reg up_drp_rwn = 'd0;
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reg [11:0] up_drp_addr = 'd0;
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reg [31:0] up_drp_wdata = 'd0;
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reg [31:0] up_drp_rdata_hold = 'd0;
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reg up_status_ovf = 'd0;
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reg up_status_unf = 'd0;
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reg [ 7:0] up_usr_chanmax = 'd0;
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reg [31:0] up_dac_gpio_out = 'd0;
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reg up_rack = 'd0;
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reg [31:0] up_rdata = 'd0;
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reg dac_sync_d = 'd0;
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reg dac_sync_2d = 'd0;
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reg [ 5:0] dac_sync_count = 'd0;
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reg dac_sync = 'd0;
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reg dac_frame_d = 'd0;
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reg dac_frame_2d = 'd0;
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reg dac_frame = 'd0;
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// internal signals
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wire up_wreq_s;
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wire up_rreq_s;
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wire up_xfer_done_s;
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wire up_status_s;
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wire up_status_ovf_s;
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wire up_status_unf_s;
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wire dac_sync_s;
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wire dac_frame_s;
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wire [31:0] up_dac_clk_count_s;
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// decode block select
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assign up_wreq_s = (up_waddr[13:8] == DAC_COMMON_ID) ? up_wreq : 1'b0;
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assign up_rreq_s = (up_raddr[13:8] == DAC_COMMON_ID) ? up_rreq : 1'b0;
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// processor write interface
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always @(negedge up_rstn or posedge up_clk) begin
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if (up_rstn == 0) begin
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up_core_preset <= 1'd1;
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up_mmcm_preset <= 1'd1;
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up_wack <= 'd0;
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up_scratch <= 'd0;
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up_mmcm_resetn <= 'd0;
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up_resetn <= 'd0;
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up_dac_sync <= 'd0;
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up_dac_par_type <= 'd0;
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up_dac_par_enb <= 'd0;
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up_dac_r1_mode <= 'd0;
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up_dac_datafmt <= 'd0;
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up_dac_datarate <= 'd0;
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up_dac_frame <= 'd0;
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up_dac_clksel <= 'd0;
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up_drp_sel <= 'd0;
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up_drp_wr <= 'd0;
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up_drp_status <= 'd0;
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up_drp_rwn <= 'd0;
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up_drp_addr <= 'd0;
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up_drp_wdata <= 'd0;
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up_drp_rdata_hold <= 'd0;
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up_status_ovf <= 'd0;
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up_status_unf <= 'd0;
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up_usr_chanmax <= 'd0;
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up_dac_gpio_out <= 'd0;
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end else begin
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up_core_preset <= ~up_resetn;
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up_mmcm_preset <= ~up_mmcm_resetn;
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up_wack <= up_wreq_s;
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if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h02)) begin
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up_scratch <= up_wdata;
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end
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if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h10)) begin
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up_mmcm_resetn <= up_wdata[1];
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up_resetn <= up_wdata[0];
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end
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if (up_dac_sync == 1'b1) begin
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if (up_xfer_done_s == 1'b1) begin
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up_dac_sync <= 1'b0;
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end
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end else if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h11)) begin
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up_dac_sync <= up_wdata[0];
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end
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if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h12)) begin
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up_dac_par_type <= up_wdata[7];
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up_dac_par_enb <= up_wdata[6];
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up_dac_r1_mode <= up_wdata[5];
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up_dac_datafmt <= up_wdata[4];
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end
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if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h13)) begin
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up_dac_datarate <= up_wdata[7:0];
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end
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if (up_dac_frame == 1'b1) begin
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if (up_xfer_done_s == 1'b1) begin
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up_dac_frame <= 1'b0;
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end
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end else if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h14)) begin
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up_dac_frame <= up_wdata[0];
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end
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if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h18)) begin
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up_dac_clksel <= up_wdata[0];
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end
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if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h1c)) begin
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up_drp_sel <= 1'b1;
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up_drp_wr <= ~up_wdata[12];
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end else begin
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up_drp_sel <= 1'b0;
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up_drp_wr <= 1'b0;
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end
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if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h1c)) begin
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up_drp_status <= 1'b1;
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end else if (up_drp_ready == 1'b1) begin
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up_drp_status <= 1'b0;
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end
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if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h1c)) begin
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up_drp_rwn <= up_wdata[12];
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up_drp_addr <= up_wdata[11:0];
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end
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if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h1e)) begin
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up_drp_wdata <= up_wdata;
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end
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if (up_drp_ready == 1'b1) begin
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up_drp_rdata_hold <= up_drp_rdata;
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end
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if (up_status_ovf_s == 1'b1) begin
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up_status_ovf <= 1'b1;
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end else if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h22)) begin
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up_status_ovf <= up_status_ovf & ~up_wdata[1];
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end
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if (up_status_unf_s == 1'b1) begin
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up_status_unf <= 1'b1;
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end else if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h22)) begin
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up_status_unf <= up_status_unf & ~up_wdata[0];
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end
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if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h28)) begin
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up_usr_chanmax <= up_wdata[7:0];
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end
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if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h2f)) begin
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up_dac_gpio_out <= up_wdata;
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end
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end
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end
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// processor read interface
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always @(negedge up_rstn or posedge up_clk) begin
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if (up_rstn == 0) begin
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up_rack <= 'd0;
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up_rdata <= 'd0;
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end else begin
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up_rack <= up_rreq_s;
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if (up_rreq_s == 1'b1) begin
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case (up_raddr[7:0])
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8'h00: up_rdata <= PCORE_VERSION;
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8'h01: up_rdata <= ID;
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8'h02: up_rdata <= up_scratch;
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8'h10: up_rdata <= {30'd0, up_mmcm_resetn, up_resetn};
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8'h11: up_rdata <= {31'd0, up_dac_sync};
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8'h12: up_rdata <= {24'd0, up_dac_par_type, up_dac_par_enb, up_dac_r1_mode,
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up_dac_datafmt, 4'd0};
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8'h13: up_rdata <= {24'd0, up_dac_datarate};
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8'h14: up_rdata <= {31'd0, up_dac_frame};
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8'h15: up_rdata <= up_dac_clk_count_s;
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8'h16: up_rdata <= dac_clk_ratio;
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8'h17: up_rdata <= {31'd0, up_status_s};
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8'h18: up_rdata <= {31'd0, up_dac_clksel};
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8'h1c: up_rdata <= {19'd0, up_drp_rwn, up_drp_addr};
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8'h1d: up_rdata <= {30'd0, up_drp_locked, up_drp_status};
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8'h1e: up_rdata <= up_drp_wdata;
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8'h1f: up_rdata <= up_drp_rdata_hold;
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8'h22: up_rdata <= {30'd0, up_status_ovf, up_status_unf};
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8'h28: up_rdata <= {24'd0, dac_usr_chanmax};
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8'h2e: up_rdata <= up_dac_gpio_in;
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8'h2f: up_rdata <= up_dac_gpio_out;
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default: up_rdata <= 0;
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endcase
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end else begin
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up_rdata <= 32'd0;
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end
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end
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end
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// resets
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ad_rst i_mmcm_rst_reg (.preset(up_mmcm_preset), .clk(up_clk), .rst(mmcm_rst));
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ad_rst i_core_rst_reg (.preset(up_core_preset), .clk(dac_clk), .rst(dac_rst));
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// dac control & status
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up_xfer_cntrl #(.DATA_WIDTH(15)) i_xfer_cntrl (
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.up_rstn (up_rstn),
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.up_clk (up_clk),
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.up_data_cntrl ({ up_dac_sync,
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up_dac_clksel,
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up_dac_frame,
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up_dac_par_type,
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up_dac_par_enb,
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up_dac_r1_mode,
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up_dac_datafmt,
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up_dac_datarate}),
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.up_xfer_done (up_xfer_done_s),
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.d_rst (dac_rst),
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.d_clk (dac_clk),
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.d_data_cntrl ({ dac_sync_s,
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dac_clksel,
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dac_frame_s,
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dac_par_type,
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dac_par_enb,
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dac_r1_mode,
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dac_datafmt,
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dac_datarate}));
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up_xfer_status #(.DATA_WIDTH(3)) i_xfer_status (
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.up_rstn (up_rstn),
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.up_clk (up_clk),
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.up_data_status ({up_status_s,
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up_status_ovf_s,
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up_status_unf_s}),
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.d_rst (dac_rst),
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.d_clk (dac_clk),
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.d_data_status ({ dac_status,
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dac_status_ovf,
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dac_status_unf}));
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// generate frame and enable
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always @(posedge dac_clk) begin
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dac_sync_d <= dac_sync_s;
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dac_sync_2d <= dac_sync_d;
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if (dac_sync_count[5] == 1'b1) begin
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dac_sync_count <= dac_sync_count + 1'b1;
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end else if ((dac_sync_d == 1'b1) && (dac_sync_2d == 1'b0)) begin
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dac_sync_count <= 6'h20;
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end
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dac_sync <= dac_sync_count[5];
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dac_frame_d <= dac_frame_s;
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dac_frame_2d <= dac_frame_d;
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dac_frame <= dac_frame_d & ~dac_frame_2d;
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end
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// dac clock monitor
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up_clock_mon i_clock_mon (
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.up_rstn (up_rstn),
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.up_clk (up_clk),
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.up_d_count (up_dac_clk_count_s),
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.d_rst (dac_rst),
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.d_clk (dac_clk));
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endmodule
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// ***************************************************************************
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// ***************************************************************************
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