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Lars-Peter Clausen 0e6cc95d0d pzsdr1/pzsdr2: audio_clkgen: Disable clock source buffer insertion 
Depending on the configuration of the clock source type of the input clock
the clocking wizard will instantiate all kinds of buffers on the input
clock signal.

For these particular projects there is no need to add any kind of buffer
since the source is already coming from a global clock buffer.  So set the
configuration accordingly.

Avoids the following warning:
	[Opt 31-32] Removing redundant IBUF since it is not being driven by a
	top-level port. i_system_wrapper/system_i/sys_audio_clkgen/inst/clkin1_ibufg
	Resolution: The tool has removed redundant IBUF. To resolve this
	warning, check for redundant IBUF in the input design.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
 		2017-04-21 13:22:33 +02:00
..
ad6676evb all: Update verilog files to verilog-2001 2017-04-13 11:59:55 +03:00
ad7616_sdz all: Update verilog files to verilog-2001 2017-04-13 11:59:55 +03:00
ad7768evb all: Update verilog files to verilog-2001 2017-04-13 11:59:55 +03:00
ad9265_fmc all: Update verilog files to verilog-2001 2017-04-13 11:59:55 +03:00
ad9434_fmc ad9434_fmc: Port redeclaration as a wire is not allowed 2017-04-20 14:33:47 +03:00
ad9467_fmc all: Update verilog files to verilog-2001 2017-04-13 11:59:55 +03:00
ad9739a_fmc all: Update verilog files to verilog-2001 2017-04-13 11:59:55 +03:00
adrv9371x adrv9371/a10soc: Integrate the avl_dacfifo into project 2017-04-21 13:27:35 +03:00
adv7511 ac701_common/adv7511: Update IP instantiations 2017-04-21 13:16:25 +03:00
arradio Makefiles: Change MMU enabling parameter for altera designs from MMU to NIOS2_MMU 2017-04-18 10:57:16 +03:00
cftl_cip cftl_cip: cleaned up some warnings 2017-04-18 10:29:20 +03:00
cftl_std cftl_std: cleaned up some warnings 2017-04-18 10:32:28 +03:00
cn0363 all: Update verilog files to verilog-2001 2017-04-13 11:59:55 +03:00
common adrv9371/a10soc: Integrate the avl_dacfifo into project 2017-04-21 13:27:35 +03:00
daq1 Makefiles: Change MMU enabling parameter for altera designs from MMU to NIOS2_MMU 2017-04-18 10:57:16 +03:00
daq2 Makefiles: Change MMU enabling parameter for altera designs from MMU to NIOS2_MMU 2017-04-18 10:57:16 +03:00
daq3 Makefiles: Change MMU enabling parameter for altera designs from MMU to NIOS2_MMU 2017-04-18 10:57:16 +03:00
fmcadc2 all: Update verilog files to verilog-2001 2017-04-13 11:59:55 +03:00
fmcadc4 all: Update verilog files to verilog-2001 2017-04-13 11:59:55 +03:00
fmcadc5 fmcadc5/vc707, lpm mode 2017-04-18 12:41:53 -04:00
fmcjesdadc1 Makefiles: Change MMU enabling parameter for altera designs from MMU to NIOS2_MMU 2017-04-18 10:57:16 +03:00
fmcomms2 fmcomms2/zc702: Fix Warning[Synth 8-2611] 2017-04-19 13:54:03 +03:00
fmcomms5 all: Update verilog files to verilog-2001 2017-04-13 11:59:55 +03:00
fmcomms7 all: Update verilog files to verilog-2001 2017-04-13 11:59:55 +03:00
fmcomms11 make updates 2017-03-20 16:05:18 -04:00
imageon imageon: ip automatic version update 2017-04-14 16:54:42 +03:00
m2k m2k: zed: Fix default HDMI clock frequency 2017-04-20 20:36:34 +02:00
motcon2_fmc motcon2_fmc: cleaned up some warnings 2017-04-18 10:33:13 +03:00
pluto pluto: cleaned up some warnings 2017-04-18 10:34:13 +03:00
pzsdr1 pzsdr1/pzsdr2: audio_clkgen: Disable clock source buffer insertion 2017-04-21 13:22:33 +02:00
pzsdr2 pzsdr1/pzsdr2: audio_clkgen: Disable clock source buffer insertion 2017-04-21 13:22:33 +02:00
scripts scripts: Created ADI_POWER_OPTIMIZATION parameter for enabling power optimizations in the implementation stage 2017-04-18 12:17:40 +02:00
usb_fx3 usb_fx3: ip automatic version update 2017-04-14 16:55:30 +03:00
usdrx1 Makefiles: Change MMU enabling parameter for altera designs from MMU to NIOS2_MMU 2017-04-18 10:57:16 +03:00
usrpe31x make updates 2017-03-20 16:05:18 -04:00
Makefile Make: Update Makefiles 2017-02-10 16:32:58 +02:00