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Istvan Csomortani 7960b00684 block_design: Update with new clock net variables 
Using the new clock net variables in all Xilinx block designs.
 		2019-06-11 18:13:06 +03:00
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common block_design: Update with new clock net variables 2019-06-11 18:13:06 +03:00
zc702 whitespace: Delete all trailing white spaces 2019-06-07 10:20:15 +03:00
zc706 whitespace: Delete all trailing white spaces 2019-06-07 10:20:15 +03:00
zcu102 block_design: Update with new clock net variables 2019-06-11 18:13:06 +03:00
Makefile Regenerate project top-level Makefiles 2018-04-11 15:09:54 +03:00