146 lines
4.8 KiB
Verilog
146 lines
4.8 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2011(c) Analog Devices, Inc.
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//
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without modification,
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// are permitted provided that the following conditions are met:
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// - Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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// - Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in
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// the documentation and/or other materials provided with the
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// distribution.
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// - Neither the name of Analog Devices, Inc. nor the names of its
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// contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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// - The use of this software may or may not infringe the patent rights
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// of one or more patent holders. This license does not release you
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// from the requirement that you obtain separate licenses from these
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// patent holders to use this software.
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// - Use of the software either in source or binary form, must be run
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// on or directly connected to an Analog Devices Inc. component.
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//
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// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
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// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
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// PARTICULAR PURPOSE ARE DISCLAIMED.
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//
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// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
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// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
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// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// ***************************************************************************
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// ***************************************************************************
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// serial data output interface: serdes(x8)
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`timescale 1ps/1ps
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module ad_serdes_clk #(
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parameter DEVICE_TYPE = 0,
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parameter DDR_OR_SDR_N = 1,
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parameter SERDES_FACTOR = 8,
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parameter MMCM_OR_BUFR_N = 1,
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parameter MMCM_CLKIN_PERIOD = 1.667,
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parameter MMCM_VCO_DIV = 6,
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parameter MMCM_VCO_MUL = 12.000,
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parameter MMCM_CLK0_DIV = 2.000,
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parameter MMCM_CLK1_DIV = 6) (
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// clock and divided clock
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input rst,
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input clk_in_p,
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input clk_in_n,
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output clk,
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output div_clk,
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output out_clk,
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output loaden,
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output [ 7:0] phase,
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// drp interface
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input up_clk,
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input up_rstn,
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input up_drp_sel,
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input up_drp_wr,
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input [11:0] up_drp_addr,
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input [31:0] up_drp_wdata,
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output [31:0] up_drp_rdata,
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output up_drp_ready,
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output up_drp_locked);
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// internal signals
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wire clk_in_s;
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// defaults
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assign loaden = 'd0;
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assign phase = 'd0;
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assign up_drp_rdata[31:16] = 'd0;
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// instantiations
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IBUFGDS i_clk_in_ibuf (
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.I (clk_in_p),
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.IB (clk_in_n),
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.O (clk_in_s));
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generate
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if (MMCM_OR_BUFR_N == 1) begin
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ad_mmcm_drp #(
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.MMCM_DEVICE_TYPE (DEVICE_TYPE),
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.MMCM_CLKIN_PERIOD (MMCM_CLKIN_PERIOD),
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.MMCM_CLKIN2_PERIOD (MMCM_CLKIN_PERIOD),
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.MMCM_VCO_DIV (MMCM_VCO_DIV),
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.MMCM_VCO_MUL (MMCM_VCO_MUL),
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.MMCM_CLK0_DIV (MMCM_CLK0_DIV),
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.MMCM_CLK0_PHASE (0.0),
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.MMCM_CLK1_DIV (MMCM_CLK1_DIV),
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.MMCM_CLK1_PHASE (0.0),
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.MMCM_CLK2_DIV (MMCM_CLK0_DIV),
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.MMCM_CLK2_PHASE (90.0))
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i_mmcm_drp (
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.clk (clk_in_s),
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.clk2 (1'b0),
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.clk_sel (1'b1),
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.mmcm_rst (rst),
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.mmcm_clk_0 (clk),
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.mmcm_clk_1 (div_clk),
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.mmcm_clk_2 (out_clk),
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.up_clk (up_clk),
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.up_rstn (up_rstn),
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.up_drp_sel (up_drp_sel),
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.up_drp_wr (up_drp_wr),
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.up_drp_addr (up_drp_addr),
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.up_drp_wdata (up_drp_wdata[15:0]),
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.up_drp_rdata (up_drp_rdata[15:0]),
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.up_drp_ready (up_drp_ready),
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.up_drp_locked (up_drp_locked));
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end
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if (MMCM_OR_BUFR_N == 0) begin
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BUFIO i_clk_buf (
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.I (clk_in_s),
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.O (clk));
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BUFR #(.BUFR_DIVIDE("4")) i_div_clk_buf (
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.CLR (1'b0),
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.CE (1'b1),
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.I (clk_in_s),
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.O (div_clk));
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assign out_clk = clk;
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end
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endgenerate
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endmodule
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// ***************************************************************************
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// ***************************************************************************
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