540 lines
16 KiB
Verilog
540 lines
16 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright (C) 2023 Analog Devices, Inc. All rights reserved.
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//
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// In this HDL repository, there are many different and unique modules, consisting
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// of various HDL (Verilog or VHDL) components. The individual modules are
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// developed independently, and may be accompanied by separate and unique license
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// terms.
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//
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// The user should read each of these license terms, and understand the
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// freedoms and responsibilities that he or she has by using this source/core.
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//
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// This core is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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// A PARTICULAR PURPOSE.
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//
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// Redistribution and use of source or resulting binaries, with or without modification
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// of this file, are permitted under one of the following two license terms:
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//
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// 1. The GNU General Public License version 2 as published by the
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// Free Software Foundation, which can be found in the top level directory
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// of this repository (LICENSE_GPL2), and also online at:
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// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
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//
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// OR
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//
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// 2. An ADI specific BSD license, which can be found in the top level directory
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// of this repository (LICENSE_ADIBSD), and also on-line at:
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// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
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// This will allow to generate bit files and not release the source code,
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// as long as it attaches to an ADI device.
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//
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module axi_ad4858 #(
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parameter FPGA_TECHNOLOGY = 0,
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parameter DELAY_REFCLK_FREQ = 200,
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parameter IODELAY_ENABLE = 1,
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parameter ID = 0,
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parameter LVDS_CMOS_N = 1,
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parameter LANE_0_ENABLE = "1",
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parameter LANE_1_ENABLE = "1",
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parameter LANE_2_ENABLE = "1",
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parameter LANE_3_ENABLE = "1",
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parameter LANE_4_ENABLE = "1",
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parameter LANE_5_ENABLE = "1",
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parameter LANE_6_ENABLE = "1",
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parameter LANE_7_ENABLE = "1",
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parameter ECHO_CLK_EN = 1,
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parameter EXTERNAL_CLK = 1
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) (
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// clocks
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input delay_clk,
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input external_clk,
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input external_fast_clk,
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// physical data interface
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input cnvs,
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input busy,
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output lvds_cmos_n,
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// cmos if signals
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output scki,
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input scko,
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input lane_0,
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input lane_1,
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input lane_2,
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input lane_3,
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input lane_4,
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input lane_5,
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input lane_6,
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input lane_7,
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// lvds if signals
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output scki_p,
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output scki_n,
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input scko_p,
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input scko_n,
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input sdo_p,
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input sdo_n,
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// AXI Slave Memory Map
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input s_axi_aclk,
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input s_axi_aresetn,
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input s_axi_awvalid,
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input [15:0] s_axi_awaddr,
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input [ 2:0] s_axi_awprot,
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output s_axi_awready,
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input s_axi_wvalid,
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input [31:0] s_axi_wdata,
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input [ 3:0] s_axi_wstrb,
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output s_axi_wready,
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output s_axi_bvalid,
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output [ 1:0] s_axi_bresp,
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input s_axi_bready,
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input s_axi_arvalid,
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input [15:0] s_axi_araddr,
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input [ 2:0] s_axi_arprot,
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output s_axi_arready,
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output s_axi_rvalid,
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output [ 1:0] s_axi_rresp,
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output [31:0] s_axi_rdata,
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input s_axi_rready,
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// Write FIFO interface
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input adc_dovf,
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output adc_valid,
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output adc_enable_0,
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output adc_enable_1,
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output adc_enable_2,
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output adc_enable_3,
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output adc_enable_4,
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output adc_enable_5,
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output adc_enable_6,
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output adc_enable_7,
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output [31:0] adc_data_0,
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output [31:0] adc_data_1,
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output [31:0] adc_data_2,
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output [31:0] adc_data_3,
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output [31:0] adc_data_4,
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output [31:0] adc_data_5,
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output [31:0] adc_data_6,
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output [31:0] adc_data_7
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);
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// localparam
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localparam [ 0:0] READ_RAW = 1'b1;
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localparam CONFIG = {18'd0, READ_RAW, 5'd0, ~LVDS_CMOS_N[0], 7'd0};
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localparam [ 7:0] ACTIVE_LANES = {
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LANE_7_ENABLE == 1 ? 1'b1 : 1'b0,
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LANE_6_ENABLE == 1 ? 1'b1 : 1'b0,
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LANE_5_ENABLE == 1 ? 1'b1 : 1'b0,
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LANE_4_ENABLE == 1 ? 1'b1 : 1'b0,
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LANE_3_ENABLE == 1 ? 1'b1 : 1'b0,
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LANE_2_ENABLE == 1 ? 1'b1 : 1'b0,
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LANE_1_ENABLE == 1 ? 1'b1 : 1'b0,
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LANE_0_ENABLE == 1 ? 1'b1 : 1'b0};
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// internal registers
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reg up_wack = 1'b0;
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reg up_rack = 1'b0;
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reg [31:0] up_rdata = 32'b0;
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reg up_status_or = 1'b0;
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reg [ 7:0] adc_reset;
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reg adc_if_reset;
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// internal signals
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wire adc_rst_s;
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wire adc_clk_s;
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wire scko_s;
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wire scko_s_p;
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wire scko_s_n;
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wire up_clk;
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wire up_rstn;
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wire up_rreq_s;
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wire [13:0] up_raddr_s;
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wire up_wreq_s;
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wire [13:0] up_waddr_s;
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wire [31:0] up_wdata_s;
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wire [31:0] up_rdata_s[0:9];
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wire [ 9:0] up_rack_s;
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wire [ 9:0] up_wack_s;
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wire [255:0] adc_data_if_s;
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wire [ 7:0] adc_enable_s;
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wire [31:0] adc_data_s[7:0];
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wire adc_valid_if;
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wire [ 7:0] adc_valid_s;
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wire crc_error;
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wire [ 7:0] adc_or;
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wire [ 7:0] up_adc_or_s;
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wire [ 7:0] up_adc_pn_err;
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wire [ 7:0] up_adc_pn_oos;
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wire [ 7:0] adc_custom_control;
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wire [ 1:0] packet_format;
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wire oversampling_en;
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wire adc_crc_enable_s;
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wire delay_rst;
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wire delay_locked;
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// defaults
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assign up_clk = s_axi_aclk;
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assign up_rstn = s_axi_aresetn;
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assign lvds_cmos_n = LVDS_CMOS_N[0];
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assign adc_enable_0 = adc_enable_s[0];
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assign adc_enable_1 = adc_enable_s[1];
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assign adc_enable_2 = adc_enable_s[2];
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assign adc_enable_3 = adc_enable_s[3];
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assign adc_enable_4 = adc_enable_s[4];
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assign adc_enable_5 = adc_enable_s[5];
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assign adc_enable_6 = adc_enable_s[6];
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assign adc_enable_7 = adc_enable_s[7];
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assign adc_valid = adc_valid_s[0];
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assign adc_data_0 = adc_data_s[0];
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assign adc_data_1 = adc_data_s[1];
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assign adc_data_2 = adc_data_s[2];
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assign adc_data_3 = adc_data_s[3];
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assign adc_data_4 = adc_data_s[4];
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assign adc_data_5 = adc_data_s[5];
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assign adc_data_6 = adc_data_s[6];
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assign adc_data_7 = adc_data_s[7];
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assign packet_format = adc_custom_control[1:0];
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assign oversampling_en = adc_custom_control[2];
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// processor read interface
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always @(negedge up_rstn or posedge up_clk) begin
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if (up_rstn == 0) begin
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up_status_or <= 'd0;
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up_wack <= 'd0;
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up_rack <= 'd0;
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up_rdata <= 'd0;
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end else begin
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up_status_or <= | up_adc_or_s;
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up_wack <= |up_wack_s;
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up_rack <= |up_rack_s;
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up_rdata <= up_rdata_s[0] |
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up_rdata_s[1] |
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up_rdata_s[2] |
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up_rdata_s[3] |
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up_rdata_s[4] |
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up_rdata_s[5] |
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up_rdata_s[6] |
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up_rdata_s[7] |
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up_rdata_s[8] |
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up_rdata_s[9];
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end
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end
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genvar i;
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generate
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if (EXTERNAL_CLK == 1'b1) begin
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assign adc_clk_s = external_clk;
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end else begin
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assign adc_clk_s = up_clk;
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end
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always @(posedge adc_clk_s) begin
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adc_if_reset <= adc_rst_s;
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end
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if (LVDS_CMOS_N == 1) begin // LVDS
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wire up_dld;
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wire [ 4:0] up_dwdata;
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wire [ 4:0] up_drdata;
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assign scki = 1'b0;
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if (ECHO_CLK_EN == 1'b1) begin
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assign scko_s_p = scko_p;
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assign scko_s_n = scko_n;
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end else begin
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assign scko_s_p = scki_p;
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assign scko_s_n = scki_n;
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end
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axi_ad4858_lvds #(
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.FPGA_TECHNOLOGY (FPGA_TECHNOLOGY),
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.DELAY_REFCLK_FREQ(DELAY_REFCLK_FREQ),
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.IODELAY_ENABLE (IODELAY_ENABLE)
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) i_ad4858_lvds_interface (
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.rst (adc_if_reset),
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.clk (adc_clk_s),
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.fast_clk (external_fast_clk),
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.adc_enable (adc_enable_s),
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.adc_crc_enable (adc_crc_enable_s),
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.packet_format_in (packet_format),
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.oversampling_en (oversampling_en),
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.scki_p (scki_p),
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.scki_n (scki_n),
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.scko_p (scko_s_p),
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.scko_n (scko_s_n),
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.sdo_p (sdo_p),
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.sdo_n (sdo_n),
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.busy (busy),
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.cnvs (cnvs),
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.adc_data (adc_data_if_s),
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.adc_valid (adc_valid_if),
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.crc_error (crc_error),
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.dev_status (),
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.up_clk (up_clk),
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.up_adc_dld (up_dld),
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.up_adc_dwdata (up_dwdata),
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.up_adc_drdata (up_drdata),
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.delay_clk (delay_clk),
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.delay_rst (delay_rst),
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.delay_locked (delay_locked));
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up_delay_cntrl #(
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.DATA_WIDTH(1),
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.BASE_ADDRESS(6'h02)
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) i_delay_cntrl (
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.delay_clk (delay_clk),
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.delay_rst (delay_rst),
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.delay_locked (delay_locked),
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.up_dld (up_dld),
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.up_dwdata (up_dwdata),
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.up_drdata (up_drdata),
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.up_rstn (up_rstn),
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.up_clk (up_clk),
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.up_wreq (up_wreq_s),
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.up_waddr (up_waddr_s),
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.up_wdata (up_wdata_s),
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.up_wack (up_wack_s[9]),
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.up_rreq (up_rreq_s),
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.up_raddr (up_raddr_s),
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.up_rdata (up_rdata_s[9]),
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.up_rack (up_rack_s[9]));
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end else begin // CMOS
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wire [ 7:0] up_dld;
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wire [39:0] up_dwdata;
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wire [39:0] up_drdata;
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assign scki_p = 1'b0;
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assign scki_n = 1'b1;
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if (ECHO_CLK_EN == 1'b1) begin
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assign scko_s = scko;
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end else begin
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assign scko_s = scki;
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end
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axi_ad4858_cmos #(
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.FPGA_TECHNOLOGY (FPGA_TECHNOLOGY),
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.DELAY_REFCLK_FREQ(DELAY_REFCLK_FREQ),
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.IODELAY_ENABLE (IODELAY_ENABLE),
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.ACTIVE_LANE (ACTIVE_LANES)
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) i_ad4858_cmos_interface (
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.rst (adc_if_reset),
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.clk (adc_clk_s),
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.adc_enable (adc_enable_s),
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.adc_crc_enable (adc_crc_enable_s),
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.packet_format (packet_format),
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.oversampling_en (oversampling_en),
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.scki (scki),
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.scko (scko_s),
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.db_i ({lane_7,
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lane_6,
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lane_5,
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lane_4,
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lane_3,
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lane_2,
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lane_1,
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lane_0}),
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.busy (busy),
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.cnvs (cnvs),
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.adc_data (adc_data_if_s),
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.adc_valid (adc_valid_if),
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.crc_error (crc_error),
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.dev_status (),
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.up_clk (up_clk),
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.up_adc_dld (up_dld),
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.up_adc_dwdata (up_dwdata),
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.up_adc_drdata (up_drdata),
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.delay_clk (delay_clk),
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.delay_rst (delay_rst),
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.delay_locked (delay_locked));
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up_delay_cntrl #(
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.DATA_WIDTH(8),
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.BASE_ADDRESS(6'h02)
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) i_delay_cntrl (
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.delay_clk (delay_clk),
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.delay_rst (delay_rst),
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.delay_locked (delay_locked),
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.up_dld (up_dld),
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.up_dwdata (up_dwdata),
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.up_drdata (up_drdata),
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.up_rstn (up_rstn),
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.up_clk (up_clk),
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.up_wreq (up_wreq_s),
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.up_waddr (up_waddr_s),
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.up_wdata (up_wdata_s),
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.up_wack (up_wack_s[9]),
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.up_rreq (up_rreq_s),
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.up_raddr (up_raddr_s),
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.up_rdata (up_rdata_s[9]),
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.up_rack (up_rack_s[9]));
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end
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// adc channels
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for (i = 0; i < 8; i=i+1) begin : channel
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always @(posedge adc_clk_s) begin
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adc_reset[i] <= adc_rst_s;
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end
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axi_ad4858_channel #(
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.CHANNEL_ID(i),
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.ACTIVE_LANE (ACTIVE_LANES)
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) i_adc_channel (
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.adc_clk (adc_clk_s),
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.adc_rst (adc_reset[i]),
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.adc_ch_valid_in (adc_valid_if),
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.adc_ch_data_in (adc_data_if_s[32*i+:32]),
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.if_crc_err (crc_error),
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.adc_enable (adc_enable_s[i]),
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.adc_valid (adc_valid_s[i]),
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.adc_data (adc_data_s[i]),
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.adc_or (adc_or[i]),
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.adc_status_header (),
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.packet_format (packet_format),
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.oversampling_en (oversampling_en),
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.up_adc_or (up_adc_or_s[i]),
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.up_adc_pn_err (up_adc_pn_err[i]),
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.up_adc_pn_oos (up_adc_pn_oos[i]),
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.up_rstn (up_rstn),
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.up_clk (up_clk),
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.up_wreq (up_wreq_s),
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.up_waddr (up_waddr_s),
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.up_wdata (up_wdata_s),
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.up_wack (up_wack_s[i]),
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.up_rreq (up_rreq_s),
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.up_raddr (up_raddr_s),
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.up_rdata (up_rdata_s[i]),
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.up_rack (up_rack_s[i]));
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end
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endgenerate
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// adc up common
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up_adc_common #(
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.ID(ID),
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.CONFIG(CONFIG)
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) i_up_adc_common (
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.mmcm_rst (),
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.adc_clk (adc_clk_s),
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.adc_rst (adc_rst_s),
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.adc_r1_mode (),
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.adc_ddr_edgesel (),
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.adc_pin_mode (),
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.adc_status ('h1),
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.adc_sync_status (1'b1),
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.adc_status_ovf (adc_dovf),
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.adc_clk_ratio (32'd1),
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.adc_start_code (),
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.adc_sref_sync (),
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.adc_sync (),
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.adc_ext_sync_arm (),
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.adc_ext_sync_disarm (),
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.adc_ext_sync_manual_req (),
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.adc_custom_control (adc_custom_control),
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.adc_sdr_ddr_n (),
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.adc_symb_op (),
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.adc_symb_8_16b (),
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.adc_num_lanes (),
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.adc_crc_enable (adc_crc_enable_s),
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.up_pps_rcounter (32'b0),
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.up_pps_status (1'b0),
|
|
.up_pps_irq_mask (),
|
|
.up_adc_ce (),
|
|
.up_status_pn_err (|up_adc_pn_err),
|
|
.up_status_pn_oos (|up_adc_pn_oos),
|
|
.up_status_or (|up_status_or),
|
|
.up_adc_r1_mode(),
|
|
.up_drp_sel (),
|
|
.up_drp_wr (),
|
|
.up_drp_addr (),
|
|
.up_drp_wdata (),
|
|
.up_drp_rdata (32'd0),
|
|
.up_drp_ready (1'd0),
|
|
.up_drp_locked (1'd1),
|
|
.adc_config_wr (),
|
|
.adc_config_ctrl (),
|
|
.adc_config_rd ('d0),
|
|
.adc_ctrl_status ('d0),
|
|
.up_usr_chanmax_out (),
|
|
.up_usr_chanmax_in (8'd8),
|
|
.up_adc_gpio_in (32'b0),
|
|
.up_adc_gpio_out (),
|
|
.up_rstn (up_rstn),
|
|
.up_clk (up_clk),
|
|
.up_wreq (up_wreq_s),
|
|
.up_waddr (up_waddr_s),
|
|
.up_wdata (up_wdata_s),
|
|
.up_wack (up_wack_s[8]),
|
|
.up_rreq (up_rreq_s),
|
|
.up_raddr (up_raddr_s),
|
|
.up_rdata (up_rdata_s[8]),
|
|
.up_rack (up_rack_s[8]));
|
|
|
|
// up bus interface
|
|
|
|
up_axi #(
|
|
.AXI_ADDRESS_WIDTH (16)
|
|
) i_up_axi (
|
|
.up_rstn (up_rstn),
|
|
.up_clk (up_clk),
|
|
.up_axi_awvalid (s_axi_awvalid),
|
|
.up_axi_awaddr (s_axi_awaddr),
|
|
.up_axi_awready (s_axi_awready),
|
|
.up_axi_wvalid (s_axi_wvalid),
|
|
.up_axi_wdata (s_axi_wdata),
|
|
.up_axi_wstrb (s_axi_wstrb),
|
|
.up_axi_wready (s_axi_wready),
|
|
.up_axi_bvalid (s_axi_bvalid),
|
|
.up_axi_bresp (s_axi_bresp),
|
|
.up_axi_bready (s_axi_bready),
|
|
.up_axi_arvalid (s_axi_arvalid),
|
|
.up_axi_araddr (s_axi_araddr),
|
|
.up_axi_arready (s_axi_arready),
|
|
.up_axi_rvalid (s_axi_rvalid),
|
|
.up_axi_rresp (s_axi_rresp),
|
|
.up_axi_rdata (s_axi_rdata),
|
|
.up_axi_rready (s_axi_rready),
|
|
.up_wreq (up_wreq_s),
|
|
.up_waddr (up_waddr_s),
|
|
.up_wdata (up_wdata_s),
|
|
.up_wack (up_wack),
|
|
.up_rreq (up_rreq_s),
|
|
.up_raddr (up_raddr_s),
|
|
.up_rdata (up_rdata),
|
|
.up_rack (up_rack));
|
|
|
|
endmodule
|