43 lines
1.4 KiB
Verilog
Executable File
43 lines
1.4 KiB
Verilog
Executable File
// ***************************************************************************
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// ***************************************************************************
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// Copyright (C) 2017, 2018, 2021, 2022 Analog Devices, Inc. All rights reserved.
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// SPDX short identifier: ADIJESD204
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module align_mux #(
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parameter DATA_PATH_WIDTH = 4
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) (
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input clk,
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input [2:0] align,
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input [DATA_PATH_WIDTH*8-1:0] in_data,
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input [DATA_PATH_WIDTH-1:0] in_charisk,
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output [DATA_PATH_WIDTH*8-1:0] out_data,
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output [DATA_PATH_WIDTH-1:0] out_charisk
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);
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localparam DPW_LOG2 = DATA_PATH_WIDTH == 8 ? 3 : DATA_PATH_WIDTH == 4 ? 2 : 1;
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wire [DPW_LOG2-1:0] align_int;
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reg [DATA_PATH_WIDTH*8-1:0] in_data_d1;
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reg [DATA_PATH_WIDTH-1:0] in_charisk_d1;
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wire [(DATA_PATH_WIDTH*8*2)-1:0] data;
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wire [(DATA_PATH_WIDTH*2)-1:0] charisk;
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always @(posedge clk) begin
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in_data_d1 <= in_data;
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in_charisk_d1 <= in_charisk;
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end
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assign data = {in_data, in_data_d1};
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assign charisk = {in_charisk, in_charisk_d1};
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assign align_int = align[DPW_LOG2-1:0];
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assign out_data = data[align_int*8 +: (DATA_PATH_WIDTH*8)];
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assign out_charisk = charisk[align_int +: DATA_PATH_WIDTH];
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endmodule
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