94 lines
3.1 KiB
Plaintext
94 lines
3.1 KiB
Plaintext
###############################################################################
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## Copyright (C) 2017, 2018, 2021 Analog Devices, Inc. All rights reserved.
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### SPDX short identifier: ADIJESD204
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###############################################################################
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<: set ComponentName [getComponentNameString] :>
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<: setOutputDirectory "./" :>
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<: setFileName [ttcl_add $ComponentName "_constr"] :>
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<: setFileExtension ".xdc" :>
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<: setFileProcessingOrder late :>
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<: set sysref_iob [get_property PARAM_VALUE.SYSREF_IOB] :>
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<: set async_clk [getBooleanValue "ASYNC_CLK"] :>
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<: set link_mode [getBooleanValue "LINK_MODE"] :>
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set_property ASYNC_REG TRUE \
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[get_cells {i_lmfc/sysref_d1_reg}] \
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[get_cells {i_lmfc/sysref_d2_reg}]
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# Make sure that the device clock to sysref skew is at least somewhat
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# predictable
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set_property IOB <=: $sysref_iob :> \
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[get_cells {i_lmfc/sysref_r_reg}]
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<: if {$async_clk} { :>
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set link_clk [get_clocks -of_objects [get_ports -quiet {clk}]]
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set device_clk [get_clocks -of_objects [get_ports -quiet {device_clk}]]
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# sync bits
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set_false_path \
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-from $link_clk \
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-to [get_cells -quiet -hier *cdc_sync_stage1_reg* \
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-filter {NAME =~ *i_all_buffer_ready_cdc* && IS_SEQUENTIAL}]
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set_property ASYNC_REG TRUE \
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[get_cells -quiet -hier *cdc_sync_stage1_reg* \
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-filter {NAME =~ *i_all_buffer_ready_cdc* && IS_SEQUENTIAL}]
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set_property ASYNC_REG TRUE \
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[get_cells -quiet -hier *cdc_sync_stage2_reg* \
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-filter {NAME =~ *i_all_buffer_ready_cdc* && IS_SEQUENTIAL}]
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# sync event i_sync_lmfc
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set_false_path -quiet \
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-from $device_clk \
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-to [get_cells -quiet -hier *cdc_sync_stage1_reg* \
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-filter {NAME =~ *i_sync_lmfc/i_sync_out* && IS_SEQUENTIAL}]
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set_property ASYNC_REG TRUE \
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[get_cells -quiet -hier *cdc_sync_stage1_reg* \
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-filter {NAME =~ *i_sync_lmfc/i_sync_out* && IS_SEQUENTIAL}]
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set_property ASYNC_REG TRUE \
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[get_cells -quiet -hier *cdc_sync_stage2_reg* \
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-filter {NAME =~ *i_sync_lmfc/i_sync_out* && IS_SEQUENTIAL}]
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set_false_path -quiet \
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-from $link_clk \
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-to [get_cells -quiet -hier *cdc_sync_stage1_reg* \
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-filter {NAME =~ *i_sync_lmfc/i_sync_in* && IS_SEQUENTIAL}]
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set_property ASYNC_REG TRUE \
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[get_cells -quiet -hier *cdc_sync_stage1_reg* \
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-filter {NAME =~ *i_sync_lmfc/i_sync_in* && IS_SEQUENTIAL}]
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set_property ASYNC_REG TRUE \
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[get_cells -quiet -hier *cdc_sync_stage2_reg* \
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-filter {NAME =~ *i_sync_lmfc/i_sync_in* && IS_SEQUENTIAL}]
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# elastic buffer distributed RAM
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set_false_path -quiet \
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-from $link_clk \
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-to [get_cells -quiet -hier *rd_data_reg* \
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-filter {NAME =~ *i_elastic_buffer* && IS_SEQUENTIAL}]
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<: if {$link_mode == 2} { :>
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# sync bits i_buffer_release_cdc 64b66b
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set_false_path \
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-from $device_clk \
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-to [get_cells -quiet -hier *cdc_sync_stage1_reg* \
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-filter {NAME =~ *i_buffer_release_cdc* && IS_SEQUENTIAL}]
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set_property ASYNC_REG TRUE \
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[get_cells -quiet -hier *cdc_sync_stage1_reg* \
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-filter {NAME =~ *i_buffer_release_cdc* && IS_SEQUENTIAL}]
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set_property ASYNC_REG TRUE \
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[get_cells -quiet -hier *cdc_sync_stage2_reg* \
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-filter {NAME =~ *i_buffer_release_cdc* && IS_SEQUENTIAL}]
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<: } :>
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<: } :>
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