39b2a2b8bb
1. Simplify the control logic by adding a state machine. The improvements are on code readability and reliability. 2.Add a flush feature which can be used to clean the data from the DMA fifo. This is useful when the DMA is programmed in cyclic mode and data transmission is stopped by dma_transfer_suspend flag The software intervention is reduced at setting the flag(dma_flush_en). Flushing can also be done when activating the raw value with dma_flush_en active. 3. Add raw value support. Through this changes a user can set the dac output to a fixed predefined value in the following two cases: 1. direct, without using the dma. 2. with dma, as a hold value. The fixed value will be kipped after a cyclic buffer is stopped by axi_dac_interpolate, through dma_transfer_suspend register/signal. The raw value ca be set and transmitted independently on each channel. The predefined value is stored in reg 0x19(0x64). For more details se the documentation available at https://wiki.analog.com/resources/fpga/docs/axi_dac_interpolate |
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| .. | ||
| Makefile | ||
| axi_dac_interpolate.v | ||
| axi_dac_interpolate_constr.xdc | ||
| axi_dac_interpolate_filter.v | ||
| axi_dac_interpolate_ip.tcl | ||
| axi_dac_interpolate_reg.v | ||
| cic_interp.v | ||
| fir_interp.v | ||
| m2k_interp.m | ||