75 lines
2.6 KiB
Verilog
75 lines
2.6 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved.
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//
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// In this HDL repository, there are many different and unique modules, consisting
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// of various HDL (Verilog or VHDL) components. The individual modules are
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// developed independently, and may be accompanied by separate and unique license
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// terms.
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//
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// The user should read each of these license terms, and understand the
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// freedoms and responsibilities that he or she has by using this source/core.
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//
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// This core is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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// A PARTICULAR PURPOSE.
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//
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// Redistribution and use of source or resulting binaries, with or without modification
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// of this file, are permitted under one of the following two license terms:
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//
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// 1. The GNU General Public License version 2 as published by the
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// Free Software Foundation, which can be found in the top level directory
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// of this repository (LICENSE_GPL2), and also online at:
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// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
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//
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// OR
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//
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// 2. An ADI specific BSD license, which can be found in the top level directory
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// of this repository (LICENSE_ADIBSD), and also on-line at:
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// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
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// This will allow to generate bit files and not release the source code,
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// as long as it attaches to an ADI device.
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//
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module cic_int #(
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parameter DATA_WIDTH = 12,
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parameter STAGE_WIDTH = 1,
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parameter NUM_STAGES = 1
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) (
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input clk,
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input [NUM_STAGES-1:0] ce,
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input [DATA_WIDTH-1:0] data_in,
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output [DATA_WIDTH-1:0] data_out
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);
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reg [DATA_WIDTH-1:0] state = 'h00;
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wire [DATA_WIDTH-1:0] sum;
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wire [DATA_WIDTH-1:0] mask;
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assign data_out = state;
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assign sum = (data_in & mask) + (state & mask);
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generate
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genvar i;
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for (i = 0; i < NUM_STAGES; i = i + 1) begin
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localparam j = NUM_STAGES - i - 1;
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localparam H = DATA_WIDTH - STAGE_WIDTH * i - 1;
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localparam L = j == 0 ? 0 : DATA_WIDTH - STAGE_WIDTH * (i+1);
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assign mask[H:L] = {{H-L{1'b1}},j != 0 ? ce[j] : 1'b1};
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always @(posedge clk) begin
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if (ce[j] == 1'b1) begin
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state[H:L] <= sum[H:L];
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end
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end
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end
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endgenerate
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endmodule
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