pluto_hdl_adi/library/axi_ad9361
Arpadi e6aa3a3b38 axi_ad9361: Fixed reorder issue in ip tcl 2020-01-13 12:25:23 +02:00
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intel axi_ad9361: make the use of Rx SSI clock optional 2019-09-27 17:52:10 +03:00
xilinx axi_ad9361:xilinx:axi_ad9361_lvds_if: fix Rx latency 2019-09-27 17:52:10 +03:00
Makefile all: Rename altera to intel 2019-06-29 06:53:51 +03:00
axi_ad9361.v axi_ad9361: make the use of Rx SSI clock optional 2019-09-27 17:52:10 +03:00
axi_ad9361_constr.sdc library/axi_ad9361: tdd false paths 2016-05-04 13:42:12 -04:00
axi_ad9361_constr.xdc axi_ad9361: Update constraint file 2017-08-04 16:20:33 +01:00
axi_ad9361_delay.tcl move/rename - delay script belongs to ad9361 2017-03-10 12:44:32 -05:00
axi_ad9361_hw.tcl scripts/adi_ip_intel: Rename the ad_alt_intf to ad_interface 2019-06-29 06:53:51 +03:00
axi_ad9361_ip.tcl axi_ad9361: Fixed reorder issue in ip tcl 2020-01-13 12:25:23 +02:00
axi_ad9361_rx.v Add FPGA info parameters flow 2019-03-30 11:26:11 +02:00
axi_ad9361_rx_channel.v license: Fix a spelling mistake 2018-04-11 15:09:54 +03:00
axi_ad9361_rx_pnmon.v license: Fix a spelling mistake 2018-04-11 15:09:54 +03:00
axi_ad9361_tdd.v license: Fix a spelling mistake 2018-04-11 15:09:54 +03:00
axi_ad9361_tdd_if.v license: Fix a spelling mistake 2018-04-11 15:09:54 +03:00
axi_ad9361_tx.v axi_ad9361: sync dac_valid to adc_valid 2019-09-27 17:52:10 +03:00
axi_ad9361_tx_channel.v axi_ad9361: Updates for ad_dds phase acc wrapper 2018-07-18 18:19:30 +03:00