111adac825
- trig signal will reset state machine - slrd_n delay will be absorbed by the axi_usb_fx3_if module, when Xilinx DMA is not ready to receive data during a packet - fx32dma_eop signals when the FX3 DMA buffer should be empty. slrd_n set high and sloe_n set low for another two clock cycles - eot_fx32dma signals the interface that the packet has been fully transfered. No need for watermark signals - added length_fx32dma and length_dma2fx3 as requested |
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README.md
HDL Reference Designs
Analog Devices Inc. HDL libraries and projects
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