48 lines
1.5 KiB
Tcl
48 lines
1.5 KiB
Tcl
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# Configurable parameters
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set SAMPLE_RATE_MHZ 1000.0
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set NUM_OF_CHANNELS 4 ; # M
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set SAMPLES_PER_FRAME 1 ; # S
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set NUM_OF_LANES 4 ; # L
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set ADC_RESOLUTION 8 ; # N & NP
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# Auto-computed parameters
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set CHANNEL_DATA_WIDTH [expr 32 * $NUM_OF_LANES / $NUM_OF_CHANNELS]
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set ADC_DATA_WIDTH [expr $CHANNEL_DATA_WIDTH * $NUM_OF_CHANNELS]
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# we have to calculate with an additional dummy channel for TIA
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set DMA_DATA_WIDTH [expr $ADC_DATA_WIDTH > 127 ? 256 : \
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$ADC_DATA_WIDTH > 63 ? 128 : 64]
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set SAMPLE_WIDTH [expr $ADC_RESOLUTION > 8 ? 16 : 8]
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# add RTL sources which will be instantiated in system_bd directly
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adi_project_files ad_fmclidar1_ebz_zcu102 [list \
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"$ad_hdl_dir/library/util_cdc/sync_bits.v" \
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"../common/util_tia_chsel.v" \
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"../common/util_axis_syncgen.v" ]
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# source all the block designs
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source $ad_hdl_dir/projects/common/zcu102/zcu102_system_bd.tcl
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source ../common/ad_fmclidar1_ebz_bd.tcl
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source $ad_hdl_dir/projects/scripts/adi_pd.tcl
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# I2C for AFE board's DAC
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create_bd_intf_port -mode Master -vlnv xilinx.com:interface:iic_rtl:1.0 iic_dac
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ad_ip_instance axi_iic afe_dac_iic
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ad_connect iic_dac afe_dac_iic/iic
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ad_cpu_interconnect 0x7c800000 afe_dac_iic
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ad_cpu_interrupt ps-12 mb-14 afe_dac_iic/iic2intc_irpt
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# System ID instance and configuration
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ad_ip_parameter axi_sysid_0 CONFIG.ROM_ADDR_BITS 9
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ad_ip_parameter rom_sys_0 CONFIG.PATH_TO_FILE "[pwd]/mem_init_sys.txt"
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ad_ip_parameter rom_sys_0 CONFIG.ROM_ADDR_BITS 9
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sysid_gen_sys_init_file
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