669a2da735
Both the sys_hps.f2sdram_clock and the sys_dma_clk.clk signal are in the same clock domain. They are both driven by the same clock. And even though qsys is capable of detecting this it seems qsys interconnect is not able to infer this and inserts a extra clock domain crossing bridge between the DMA and the HPS AXI system memory interface. To avoid this connect the sys_dma_clk.clk to the sys_hps.f2sdram_clock so that all components are driven by the same qsys clock signal. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> |
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| .. | ||
| a10soc_plddr4_assign.tcl | ||
| a10soc_plddr4_dacfifo_qsys.tcl | ||
| a10soc_system_assign.tcl | ||
| a10soc_system_qsys.tcl | ||