Istvan Csomortani ac2e5a9dac constraints: Update constraints ... Xilinx recommends that all synchronizer flip-flops have their ASYNC_REG property set to true in order to preserve the synchronizer cells through any logic optimization during synthesis and implementation.		2017-02-24 13:43:32 +02:00
..
a5gt	fmcjesdadc1/a5gt- hard placement of ddr hr/qr registers	2017-02-17 15:21:33 -05:00
a5soc	Make: Update Makefiles	2017-02-10 16:32:58 +02:00
common	fmcjesdadc1/a5gt- use xilinx setup 2-dma	2016-12-22 14:14:21 -05:00
kc705	constraints: Update constraints	2017-02-24 13:43:32 +02:00
vc707	constraints: Update constraints	2017-02-24 13:43:32 +02:00
zc706	constraints: Update constraints	2017-02-24 13:43:32 +02:00
Makefile	Makefiles: Update makefiles to include the nerw axi_gpreg / util_mfifo libraries	2015-11-10 09:32:50 +02:00